• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.472-485
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• 1989

This paper represents the occurrence structure of the timing variation of TV horizontal synchronizing pulse(H-sync pulse) in mobile TV reception. Fluttering ghost is caused by timing varations of the H-sync pulse and is due to frequency elective fading in a multipath propagation envoronment. H-sync timing fluctuations, and hence, fluttering ghost are directly correlated with the multipath parameters, i.e., H-sync timing fluctuations reflect well the severity of the multipath environment. The occurrence structure of H-sync timtng fluctuation is analysed theoretically in relation to the multipath environnment. The occurrence structure of H-sync timing fluctuation is analysed theoretically in relation to the multipath parameters, assuming the two-ray propagation model. The H-sync timing fluctuation occurs with the variation in relative phase and /or D/U variation of long-delayed multipath waves.

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1387-1394
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• 2011

In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

• Speech Sciences
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• v.7 no.3
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• pp.87-98
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• 2000

Timing in speech is determined by many factors. In this paper, we introduce and discuss some factors that have generally been regarded as important in speech timing. They include stress, syllable structure, consonant insertion or deletion, tempo, lengthening at clause, phrase and word boundaries, preconsonantal vowel shortening, and compensation between segments or within phonological units (e.g., word, foot), compression due to the increase of syllables in word or foot level, etc. and each of them may playa crucial role in the structuring of speech timing in a language. But some of these timing factors must interact with each other rather than be independent and the effects of each factor on speech timing will vary from language to language. On the other hand, there could well be many other factors unknown so far. Finding out and investigating new timing factors and reinterpreting the already-known timing factors should enhance our understanding of timing structures in a given language or languages.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.235-237
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• 2002

As the integrated circuit technology gets developed, a circuit size of more than thousands of transistors becomes normal. A hierarchical design is unavoidable due to a huge circuit size. It is important how we can consider hierarchical structure in circuit delay analysis. In this paper we present an accurate method to analyze the delay of circuit with hierarchical structure. Adding the notion of global false path to the hierarchical timing analysis performs more accurate timing analysis.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.487-489
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• 2005

This paper proposes a symbol timing recovery method that is simple in structure and can provide high speed symbol synchronization. Transmitter and receiver are not synchronized in communication systems using digital modulation. Receiver should search the timing variation of transmitter continuously. The proposed timing recovery method searches sample position by comparing previous sample value with next sample value. This method can be applied to digital and optical transceivers with high data rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.31-38
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• 2012

In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.6
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• pp.1554-1566
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• 1996

In this paper, a new symbol timing algorithm for a magnetic recording system as HDD, is proposed. Above all, the Lorentzian channel model applied, the distortion and the attenuation problems of playback signals at high speed and storage density were considered. The structure and the operation of popular data detectors for HDD were understood, and the adopted symbol timing algorithm were profoundly analyzed. On the basis of these understanding and analysis, a new symbol timing algorithm for high density HDD was proposed, and the performance evaluation of this proposed algorithm was done.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1948-1951
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• 2002

In this paper, we propose a chip timing recovery algorithm that is robust to frequency offset and time variant fading environments for DS/CDMA. The proposed structure is a modified non-coherent Delay Locked Loop (DLL) that employs a decimator. Analytical expression for the proposed non-coherent DLL S-curve and steady-state timing jitter is derived and confirmed by computer simulation. The results show that the proposed structure can reduce a steady-state timing jitter of the regenerated spreading code replica to frequency offset and time-variant fading in mobile radio channel, especially in very low SNR.