• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2204-2212
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• 1999

In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.2
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• pp.135-146
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• 2022

In GNSS, the structure of the navigation message has been improved to increase the flexibility of data addition and transmission, and the robustness of message reception in a low SNR environment. GNSS signals currently being broadcast have a different message structure from each other, and the structure can be largely classified into the fixed structure, the packetized structure, and the packetized and fixed pattern structure. This paper analyzes the features of these three types of structures and compares the performance using the indicators. It can be seen that the performance after adopting the packetized structure is superior to those of other structures. In particular, there has been remarkable improvement in terms of the message management and transmission efficiency.

• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.61-68
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• 1995

The performance of event-driven logic simulation frequently used for VLSI design verification depends on the data structures for event queues. This paper improves the existing Timing Wheel as a data structure for an event queue. In case of the use of B+ tree, an efficient node degree is also presented based on the experiment results. A new Timing Wheel index structure, which eliminates the insertion and deletion overhead of B+ tree, is proposed and analyzed.

• The Korean Journal of Financial Management
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• v.25 no.2
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• pp.33-68
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• 2008

The purpose of this paper is to test the market timing hypothesis and impact of macro economic variables on capital structure choice as well as the traditional static trade-off and pecking order theories of capital structure in a integrated framework. Through a two stage test of target capital structure and capital structure choice, none of theories was consistently supported, but most of them were partly supported. In the first stage analysis of target ratio, coefficients of firm-specific variables generally supported the predictions of pecking order theory rather than those of the static trade-off theory. However, the result of the second stage test on capital structure choice supported the hypothesis of the static trade-off theory, which claims that firms usually set and pursue the target leverage ratio. Further, the result of the seconde stage shows that a simple pecking oder theory does not hold because firms with deficit of internal fund tend to issue bonds rather than stocks to raise outside fund. Also, the result indicates that the market timing hypothesis holds because firms with over-valued stocks tend to issue stocks rather than bonds. However, contrary to Korajczyk and Levy(2003), the impact of macro economic variables such as term or credit spreads on capital structure choice was negligible, and the impact of macro economic and market timing hypothesis variables were not greater in financially unconstrained firms as Korajczyk and Levy(2003) suggested.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.3
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• pp.19-30
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• 2007

In this paper, we propose low-complexity implementation of orthogonal frequency division multiple access (OFDMA) timing delay detector with multiple receive antennas for broadband wireless access (BWA). First, in order to reduce the computational complexity, the detection structure which rotates the phase of the received ranging symbols is introduced. Second, we propose the detection structure with the N-point/M-interval fast Fourier transform structure and a frequency-domain average-power estimator for complexity reduction without sacrificing the system performance. Finally, simulation results for the proposed structures and complexity comparison of the existing structure with the proposed detectors are presented.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.451-453
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• 2005

In this paper, a preamble structure and a timing synchronization method for 802.16e based system are developed. The performances of the timing offset estimation in multipath fading channel is compared in terms of absolute mean. The simulation result shows that the proposed method has smaller mean.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.771-774
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• 1999

This paper presents a new timing structure for real time communications and its performance analysis. The cycle time consists of several "one time slot" which may be an interval defined by a synchronous traffic part followed by an asynchronous traffic part. If a station receives a token within a synchronous interval, it transmits its synchronous message if any, otherwise it may transmit an asynchronous message. This scheme is different from usual allocation schemes which divide one cycle into alternating synchronous and asynchronous subslots. This protocol is designed to prevent low priority messages from delaying too much due to lots of high priority messages. We propose the algorithm and show its justification by simulation.

• Speech Sciences
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• v.8 no.1
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• pp.77-91
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• 2001

This paper investigates the timing of Korean spoken in a news-reading speech style in order to improve the naturalness of durations used in Korean speech synthesis. Each segment in a corpus of 671 read sentences was annotated with 69 segmental and prosodic features so that the measured duration could be correlated with the context in which it occurred. A CART model based on the features showed a correlation coefficient of 0.79 with an RMSE (root mean squared prediction error) of 23 ms between actual and predicted durations in reserved test data. These results are comparable with recent published results in Korean and similar to results found in other languages. An analysis of the classification tree shows that phrasal structure has the greatest effect on the segment duration, followed by syllable structure and the manner features of surrounding segments. The place features of surrounding segments only have small effects. The model has application in Korean speech synthesis systems.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.