• 전자공학회논문지A
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• 제33A권6호
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• 한국통신학회논문지
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• 제14권5호
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• pp.472-485
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• 1989

광대역 화상정보신호(TV방송파)의 이동수신에 의한 화상품질영화는 고정수신의 경우와는 전혀 다른 상황을 타나내며, 이동체의 이동과 더불어 시시각각 복잡하게 변화한다. 본 논문에서는 야외 및 실내에서의 기초적 실험에 의해 텔레비 이동수신에서 Fluttering ghost가 화상품질열화원인중 가장 중요하다고 생각하여, 그 발생원인과 특성을 조사했다. Fluttering ghost는 텔레비 수상기에서 재생되는 수평동기펄스의 동기시각이 다중파간섭 페이딩에 의해 불안정하게 변동하므로서 발생한다는 것을 알았다. 따라서, H-sync pulse timing의 다중파 조건에 대한 변화를 이론적으로 해석하고 그 특성을 밝혀 동기시간변동의 조건과 원인을 밝혔다.

• ETRI Journal
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• 제30권4호
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• 한국산학기술학회논문지
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• 제12권3호
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• pp.1387-1394
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• 2011

이 논문에서는 OFDM Modem의 심볼 타이밍 옵셋 동기화 블록에 대한 저면적 구조를 제안한다. 심볼 타이밍 동기화 블록에서의 곱셈연산을 디지털 필터 구조의 개념을 도입하여 저면적 구조를 유도하였다. 즉 곱셈연산을 CSD(Canonic Signed Digit) 방식과 CSS(Common Sub-expression Sharing) 방식의 덧셈기를 사용한 구조를 제안하였다. 제안 구조에 대한 Verilog-HDL 코딩과 합성을 통하여 $0.264mm^2$로 구현하였으며, 이는 기존 구조의 $0.723mm^2$와 비교하여 63.54%의 구현 면적 감소를 달성하였다. 따라서 제안된 구조는 OFDM 시스템의 심볼 타이밍 동기화기에 효율적으로 사용 될 수 있을 것이다.

• 음성과학
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• 제7권3호
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• pp.87-98
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• 2000

Timing in speech is determined by many factors. In this paper, we introduce and discuss some factors that have generally been regarded as important in speech timing. They include stress, syllable structure, consonant insertion or deletion, tempo, lengthening at clause, phrase and word boundaries, preconsonantal vowel shortening, and compensation between segments or within phonological units (e.g., word, foot), compression due to the increase of syllables in word or foot level, etc. and each of them may playa crucial role in the structuring of speech timing in a language. But some of these timing factors must interact with each other rather than be independent and the effects of each factor on speech timing will vary from language to language. On the other hand, there could well be many other factors unknown so far. Finding out and investigating new timing factors and reinterpreting the already-known timing factors should enhance our understanding of timing structures in a given language or languages.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.235-237
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• 2002

As the integrated circuit technology gets developed, a circuit size of more than thousands of transistors becomes normal. A hierarchical design is unavoidable due to a huge circuit size. It is important how we can consider hierarchical structure in circuit delay analysis. In this paper we present an accurate method to analyze the delay of circuit with hierarchical structure. Adding the notion of global false path to the hierarchical timing analysis performs more accurate timing analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.487-489
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• 2005

This paper proposes a symbol timing recovery method that is simple in structure and can provide high speed symbol synchronization. Transmitter and receiver are not synchronized in communication systems using digital modulation. Receiver should search the timing variation of transmitter continuously. The proposed timing recovery method searches sample position by comparing previous sample value with next sample value. This method can be applied to digital and optical transceivers with high data rate.

• 대한전자공학회논문지SD
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• 제49권2호
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• pp.31-38
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• 2012

이 논문에서는 IEEE 802.11a OFDM MODEM SoC용 타이밍 동기화 블록에 대한 저면적 구조를 제안한다. IEEE 802.11a의 타이밍 동기화 블록은 큰 구현 면적을 필요로 한다. 제안된 자기 상관 방식의 타이밍 동기화 블록 구조는 전치 직접형 필터 구조를 사용하여 곱셈 연산을 최소화하였다. 또한 CSD(Canonic Signed Digit) 계수를 이용하는 기술과 Common Sub-expression Sharing 기술을 적용하여 곱셈연산을 저면적으로 구현하였다. 제안된 타이밍 동기화 블록 구조에 대하여 Verilog-HDL 코딩과 0.13 micron 공정을 사용하여 합성한 결과, 기존 구조와 비교하여 22.7%의 구현 면적 감소 효과를 얻을 수 있었다.

• 한국통신학회논문지
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• 제21권6호
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• pp.1554-1566
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• 1996

In this paper, a new symbol timing algorithm for a magnetic recording system as HDD, is proposed. Above all, the Lorentzian channel model applied, the distortion and the attenuation problems of playback signals at high speed and storage density were considered. The structure and the operation of popular data detectors for HDD were understood, and the adopted symbol timing algorithm were profoundly analyzed. On the basis of these understanding and analysis, a new symbol timing algorithm for high density HDD was proposed, and the performance evaluation of this proposed algorithm was done.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1948-1951
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• 2002

In this paper, we propose a chip timing recovery algorithm that is robust to frequency offset and time variant fading environments for DS/CDMA. The proposed structure is a modified non-coherent Delay Locked Loop (DLL) that employs a decimator. Analytical expression for the proposed non-coherent DLL S-curve and steady-state timing jitter is derived and confirmed by computer simulation. The results show that the proposed structure can reduce a steady-state timing jitter of the regenerated spreading code replica to frequency offset and time-variant fading in mobile radio channel, especially in very low SNR.