• Title/Summary/Keyword: Time graph

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Switching Element Disjoint Multicast Scheduling for Avoiding Crosstalk in Photonic Banyan-Type Switching Networks(Part I):Graph Theoretic Analysis of Crosstalk Relationship (광 베니언-형 교환 망에서의 누화를 회피하기 위한 교환소자를 달리하는 멀티캐스트 스케줄링(제1부):누화 관계의 그래프 이론적 분석)

  • Tscha, Yeong-Hwan
    • Journal of KIISE:Information Networking
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    • v.28 no.3
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    • pp.447-453
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    • 2001
  • In this paper, we consider the scheduling of SE(switching element)-disjoint multicasting in photonic Banyan-type switching networks constructed with directional couplers. This ensures that at most, one connection holds each SE in a given time thus, neither crosstalk nor blocking will arise in the network. Such multicasting usually takes several routing rounds hence, it is desirable to keep the number of rounds(i.e., scheduling length) to a minimum. We first present the necessary and sufficient condition for connections to pass through a common SE(i.e., make crosstalk) in the photonic Banyan-type networks capable of supporting one-to-many connections. With definition of uniquely splitting a multicast connection into distinct subconnections, the crosstalk relationship of a set of connections is represented by a graph model. In order to analyze the worst case crosstalk we characterize the upper bound on the degree of the graph. The successor paper(Part II)[14] is devoted to the scheduling algorithm and the upper bound on the scheduling length. Comparison with related results is made in detail.

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An Algorithm on Function Hazard Elimination for Asynchronous Circuit Synthesis (비동기 회로 합성을 위한 펑션 해저드 제거 알고리듬)

  • 유광기;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.47-55
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    • 1999
  • In this paper, a new function hazard elimination algorithm is proposed for asynchronous circuit synthesis. In previous approach, function hazard is eliminated by using state graph which is obtained from the state assignment on STG(signal transition graph) representing transition relationship among signals. These algorithms can use conventional hazard removal and synthesis method applied in synchronous system, but it has much computational complexity and takes much time to handle the state graph. Although some hazard elimination algorithm from STG were proposed, it could not reduce the area overhead due to the addition of new signals. The proposed algorithm eliminate function hazard directly on STG and also control the number of minterms and product-term of added signal in order to minimize the area overhead. Experimental results on benchmark data shows that overall circuit area after hazard elimination is decreased about 15% on the average than that of previous method.

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Face Relation Feature for Separating Overlapped Objects in a 2D Image (2차원영상에서 가려진 물체를 분리하기 위한 면관계 특징)

  • Piljae Song;Park, Hongjoo;Hyungtai Cha;Hernsoo Hahn
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.1
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    • pp.54-68
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    • 2001
  • This paper proposes a new algorithm that detects and separates the occluding and occluded objects in a 2D image. An input image is represented by the attributed graph where a node corresponds to a surface and an arc connecting two nodes describes the adjacency of the nodes in the image. Each end of arc is weighted by relation value which tells the number of edges connected to the surface represented by the node in the opposite side of the arc. In attributed graph, homogeneous nodes pertained to a same object always construct one of three special patterns which can be simply classified by comparison of relation values of the arcs. The experimental results have shown that the proposed algorithm efficiently separates the objects overlapped arbitrarily, and that this approach of separating objects before matching operation reduces the matching time significantly by simplifying the matching problem of overlapped objects as the one of individual single object.

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Static Control Flow Analysis of Binary Codes (이진 코드의 정적 제어 흐름 분석)

  • Kim, Ki-Tae;Kim, Je-Min;Yoo, Weon-Hee
    • The Journal of the Korea Contents Association
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    • v.10 no.5
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    • pp.70-79
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    • 2010
  • We perform static program analysis for the binary code. The reason you want to analyze at the level of binary code, installed on your local computer, run the executable file without source code. And the reason we want to perform static analysis, static program analysis is to understand what actions to perform on your local computer. In this paper, execution flow graph representing information such as the execution order among functions and the flow of control is generated. Using graph, User can find execution flow of binary file and calls of insecure functions at the same time, and the graph should facilitate the analysis of binary files. In addition, program to be run is ensured the safety by providing an automated way to search the flow of execution, and program to be downloaded and installed from outside is determined whether safe before running.

A Practical RWA Algorithm-based on Lookup Table for Edge Disjoint Paths (EDP들의 참조 테이블을 이용한 실용적 인 경로 설정 및 파장 할당 알고리즘)

  • 김명희;방영철;정민영;이태진;추현승
    • Journal of KIISE:Information Networking
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    • v.31 no.2
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    • pp.123-130
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    • 2004
  • Routing and wavelength assignment(RWA) problem is an important issue in optical transport networks based on wavelength division multiplexing(WDM) technique. It is typically solved using a combination of linear programming and graph coloring, or path selection based graph algorithms. Such methods are either complex or make extensive use of heuristics. In this paper we propose a novel and efficient approach which basically obtains the maximum edge disjoint paths (EDPs) for each source-destination demand pair. And those EDPs obtained are stored in Lookup Table and used for the update of weight matrix. Routes are determined in order by the weight matrix for the demand set. The comprehensive computer simulation shows that the Proposed algorithm uses similar or fewer wavelengths with significantly less execution time than bounded greedy approach (BGA) for EDP which is currently known to be effective in practice.

Construction of Global State Transition Graph for Verifying Telecommunications Software Specifications written in Message Chart (MSC로 기술된 통신소프트웨어 명세의 검증을 위한 전체 상태 전이 그래프 생성)

  • Kim, Byeong-Man;Kim, Hyeon-Su;Sin, Yun-Sik
    • Journal of KIISE:Software and Applications
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    • v.26 no.12
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    • pp.1428-1444
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    • 1999
  • MSC는 ITU에 의해 표준화된, 병행 시스템의 명세를 기술하기 위한 그래픽 형태와 텍스트 형태를 제공하는 언어로서 실시간 시스템 특히 통신 교환 시스템의 특성을 기술하기 위해 자주 사용된다. 통신 시스템이 제대로 동작함을 보이기 위해서는 정형적인 방법을 사용하여 시스템 행위를 검증할 필요가 있다. 통신 소프트웨어를 검증하는 방법 중 하나의 방법으로 유한 상태를 기반으로 하는 방법이 있다. 유한 상태를 기반으로 하는 방법에서는 먼저 시스템 명세에 해당하는 전체 상태 전이 그래프를 생성한 후 이를 바탕으로 model-checking 등의 방법을 사용하여 시스템의 특성을 검증한다. 본 논문에서는 MSC로 기술된 통신 소프트웨어 명세로부터 전체 상태 전이 그래프를 생성하는 방법에 초점을 맞추었다. 시스템 명세에 해당하는 상태 전이 그래프를 생성하기 위해 보다 직관적으로 MSC의 의미론을 표현할 수 있고, 또한 쉽게 전체 상태 전이 그래프를 생성할 수 있는 행위 종속 그래프를 제안하였다. MSC 명세는 일단 행위 종속 그래프로 변환이 되고 이 행위 종속 그래프를 이용하여 전체 상태 전이 그래프가 생성된다.Abstract Message Sequence Chart (MSC) standardized by International Telecommunication Union is a graphical and textual language for describing the specification of concurrent systems. It is frequently used both formally and informally for specifying the behavior of real-time systems, in particular telecommunication switching systems. To ensure that a communication system operates properly, the verification process showing the correctness of system's behavior formally is necessary. One of the verification methods is a finite-state method. In the finite-state method, the global state transition graph (GSTG) is constructed and then safety and liveness properties of systems are verified through a well-known method such as model checking. In this paper, we forcus on the construction of GSTG from the specifications of telecommunication software written in MSC. We suggest Action Dependency Graph (ADG) which can present the semantics of MSC intuitively and also provide a GSTG construction method from ADG. MSC specifications are translated to ADGs and, in turns, the GSTGs are constructed by using these ADGs.

Major gene interactions effect identification on the quality of Hanwoo by radial graph (방사형그래프를 활용한 한우의 품질관련 주요 유전자 상호작용 효과 규명)

  • Lee, Jea-Young;Bae, Jae-Young;Lee, Jin-Mok;Oh, Dong-Yep;Lee, Seong-Won
    • Journal of the Korean Data and Information Science Society
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    • v.24 no.1
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    • pp.151-159
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    • 2013
  • It is well known that disease of human and economic traits of livestock are affected a lot by gene combination effect rather than a single gene effect. But existing methods have disadvantages such as heavy computing, many expenses and long time. In order to overcome those drawbacks, SNPHarvester was developed to find the main gene combinations among the many genes. In this paper, we used the superior gene combination which are related to the quality of the Korean beef cattle among sets of SNPs by SNPHarvester, and identified the superior genotypes using radial graph which can enhance various qualities of Korean beef among selected SNP combinations.

Development of a Data Structure for Effective Monitoring of Power Plant Start-up Sequences (화력 발전소의 기동 시퀀스 진행 모니터링을 위한 자료구조 개발)

  • Lee, Seung-Chul;Han, Seung-Woo;Kim, Seung-Jin
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.12
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    • pp.224-232
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    • 2009
  • Power plant start-up is a complicate process involving hundreds of operations that should be performed either automatically or manually. Several major operations should be proceeded in parallel and each major operation is again broken down into detailed operations that must be carried out in a strict sequence. Even though most of the operations are automated, still substantial portions of the operations are carried out manually and the operational status should be monitored by the crew members, which are quite stressful tasks to be performed in real time. In this paper, a data structure called an Event Sequence Monitoring Graph(ESMG) is proposed for monitoring a sequence of events involved in the power plant start-up process. The ESMG is currently being applied to a thermal power plant with a rated output of 500MW. An application example is shown with the boiler feed water pump system start-up process, which exhibits a good potential for future applications.

The Dynamic Interface Representation of Web Sites using EMFG (EMFG를 이용한 웹사이트의 동적 인터페이스 표현)

  • Kim, Eun-Sook;Yeo, Jeong-Mo
    • The KIPS Transactions:PartD
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    • v.15D no.5
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    • pp.691-698
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    • 2008
  • Web designers generally use a story board, a site map, a flow chart or the combination of these for representing web sites. But these methods are difficult to represent the entire architecture of a web site, and may be not adaptive for describing the detail flow of web pages. To solve these problems to some degree, there were works using EMFG(Extended Mark Flow Graph) recently. However the conventional EMFG representation method is not adaptive to represent the dynamic interface of web sites because that cover only the static parts of a web site. Internet utilization is rapidly growing in our life and we cannot imagine the worlds of work, study and business without internet. And web sites recently have not only more complex and various architecture but also web pages containing the dynamic interface. Therefore we propose the representation method of these web sites - for example, a web site containing varying pages with time and varying page status or contents with mouse operations - using EMFG. We expect our work to be help the design and maintenance of web sites.

Synthesis of Asynchronous Circuits from Free-Choice Signal Transition Graphs with Timing Constraints (시간 제한 조건을 가진 자유 선택 신호 전이 그래프로부터 비동기 회로의 합성)

  • Jeong, Seong-Tae;Jeong, Seok-Tae
    • The KIPS Transactions:PartA
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    • v.9A no.1
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    • pp.61-74
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    • 2002
  • This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.