• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.319-323
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• 2003

In this paper, we propose a hybrid transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater channel environments. It is designed in the digital domain except for amplifiers and implemented by using a multiple digital signal processors (DSPs) system. The digital modulation technique is quadrature phase shift keying (QPSK) and frame synchronization is an energy (non-coherent) detection scheme based on the quadrature receiver structure. DSP implementation is based on block data parallel architecture (BDPA). We shaw experimental results in th? underwater anechoic basin at KRISO. The results indicate that the frame synchronization is performed without PLL. Also, we shaw that the adaptive equalizer can compensate frame synchronization error and the correction capability is dependent on the length of equalizer.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.2
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• pp.129-137
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• 2016

To identify the cause of the error and maintain the health of system, an administrator usually analyzes event log data since it contains useful information to infer the cause of the error. However, because today's systems are huge and complex, it is almost impossible for administrators to manually analyze event log files to identify the cause of an error. In particular, as OpenStack, which is being widely used as cloud management system, operates with various service modules being linked to multiple servers, it is hard to access each node and analyze event log messages for each service module in the case of an error. For this, in this paper, we propose a novel message-based log analysis method that enables the administrator to find the cause of an error quickly. Specifically, the proposed method 1) consolidates event log data generated from system level and application service level, 2) clusters the consolidated data based on messages, and 3) analyzes interrelations among message groups in order to promptly identify the cause of a system error. This study has great significance in the following three aspects. First, the root cause of the error can be identified by collecting event logs of both system level and application service level and analyzing interrelations among the logs. Second, administrators do not need to classify messages for training since unsupervised learning of event log messages is applied. Third, using Dynamic Time Warping, an algorithm for measuring similarity of dynamic patterns over time increases accuracy of analysis on patterns generated from distributed system in which time synchronization is not exactly consistent.

• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.51-56
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• 2009

Time synchronization algorithm in wireless sensor networks is essential to various applications such as object tracking, data encryption, duplicate detection, and precise TDMA scheduling. This paper describes CDRS that is a time synchronization algorithm using the Clock Drift rate and Reference Signals between two sensor nodes. CDRS is composed of two steps. At first step, the time correction is calculated using offset and the clock drift rate between the two nodes based on the LTS method. Two nodes become a synchronized state and the time variance can be compensated by the clock drift rate. At second step, the synchronization node transmits reference signals periodically. This reference signals are used to calculate the time difference between nodes. When this value exceeds the maximum error tolerance, the first step is performed again for resynchronization. The simulation results on the performance analysis show that the time accuracy of the proposed algorithm is improved, and the energy consumption is reduced 2.5 times compared to the time synchronization algorithm with only LTS, because CDRS reduces the number of message about 50% compared to LTS and reference signals do not use the data space for timestamp.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9A
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• pp.868-877
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• 2006

Sensor network applications need synchronized time to the highest degree such as object tracking, consistent state updates, duplicate detection, and temporal order delivery. In addition, reliability issues and fault tolerance in sophisticated sensor networks have become a critical area of research today. In this paper, we proposed a fault tolerant clock management scheme in sensor networks considering two cases of fault model such as network faults and clock faults. The proposed scheme restricts the propagation of synchronization error when there are clock faults of nodes such as rapid fluctuation, severe changes in drift rate, and so on. In addition, it handles topology changes. Simulation results show that the proposed method has about $1.5{\sim}2.0$ times better performance than TPSN in the presence of faults.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.15-21
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• 2007

In this paper, we propose a technique of a practical symbol acquisition and tracking using a low complex ADC and simple digital circuits for noncoherent asynchronous impulse-radio-based Ultra Wideband (IR-UWB) receiver based on energy detection. Compared to previous approaches of detecting an exact acquisition time that require much hardware resource, the proposed technique is to detect the target symbol by finding the symbol acquisition interval per symbol with a target symbo, thus the complexity of the complete signal processing and power consumption by ADC are reduced. To do this, we define the bit decision window (BDW) and analyze the relation between SNR, hardware resource, size of BDW and BER(Bit Error Rate). Using the results, the optimum BDW size for the minimum BER with limited hardware resource is selected. The proposed synchronization technique is verified with an aid of a simulator programmed by considering practical impulse channels.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.1
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• pp.31-38
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• 1991

A direct digital control technique of a current source using the phase-controlled rectifier is presented. A digital firing technique without sensing the line voltage is proposed. This scheme generates firing pulses directly from error signal between command and output voltage. Thus the phase detection transformers filters and zero-crossing detector are unnecessary. The synchronism is modeled and analized. Also a software synchronization algorithm is presented without a look up table and controls the system in real time with fast dynamic characteristics. Using the single-chip microprocessor 8097BH, the direct digital control is implemented with minimal hardware structure. Using the time-weighted performance index, the optimal discrete IPM control technique is also proposed to control the current of the PCR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5A
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• pp.267-275
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• 2003

In UMTS terminal modem uses 3 step search procedure for initial cell search, which comprises 1) slot synchronization, 2) code group identification and frame synchronization, and 3) scrambling-code identification. The performance of initial cell search procedure depends on search parameters like observation time and threshold. The purpose of this paper is to get the optimal observation time and threshold of each step for minimum mean acquisition time. In this paper we induce mean detection time of each step and mean acquisition timefrom the model of 3 step search procedure using state diagram. Also we propose initial cell search algorithm which utilize window search method against initial oscillator error, and select an appropriate observation time and threshold of each step by the analysis of simulation and induced result. It is shown that the mean acquisition time in multipath fading channel can be shorter than 500ms by using the determined observation time and threshold of each step.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1B
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• pp.24-33
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• 2002

The cell search scheme for W-CDMA consists of the following three stages: slot synchronization(1st stage), group identification and frame boundary detection(2nd stage), and long code identification(3rd stage). The performance of the cell search when a mobile station is switched on, which is referred to as initial cell search, is decreased by the initial frequency and timing error. In this paper, we propose the pipeline structured initial cell search scheme using time trackers to compensate for the impact of the initial timing error in the stage 2 and stage 3. The simulation results show that the performance of the proposed scheme is maximal 1.5dB better than that of the conventional one when the initial timing error is near ${\pm}T_c$/2.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.619-625
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• 2009

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.