• Journal of Positioning, Navigation, and Timing
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• v.9 no.4
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• pp.397-403
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• 2020

In order to synchronize a remote system time to the reference time like Coordinated Universal Time (UTC), it is required to compare the time difference between the two clocks. The time comparison data may have some outliers and the time synchronization performance can be significantly degraded if the outliers are not removed. Therefore, it is required to employ an effective outlier detection algorithm for keeping high accurate system time. In this paper, an outlier detection method is presented for the time difference data of GNSS time transfer receivers. The time difference data between the system time and the GNSS usually have slopes because the remote system clock is under free running until synchronized to the reference clock time. For investigating the outlier detection performance of the proposed algorithm, simulations are performed by using the time difference data of a GNSS time transfer receiver corrected to a free running Cesium clock with intentionally inserted outliers. From the simulation, it is investigated that the proposed algorithm can effectively detect the inserted outliers while conventional methods such as modified Z-score and adjusted boxplot cannot. Furthermore, it is also observed that the synchronization performance can be degraded to more than 15% with 20 outliers compared to that of original data without outliers.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.331-335
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• 2010

Previous low-energy time synchronization methods have mainly focused on reducing the number of transmission or reception packets. However, this paper proposes a method that reduces the percentage of time a node has to be awake (the duty cycle), assuming that a periodic sleep-wake cycle is used to conserve energy. Based on our experience with actual WSN devices, a system model is proposed, and the potential performance of the proposed method, with different parameter values, is analyzed. To further demonstrate the feasibility of our method, experiments were conducted using nine WSN devices in a $3{\times}3$ grid network topology. The results show the average synchronization error is 107.57 $\mu{s}$ in duty cycle 5% and synchronization period 10 sec, and 130 $\mu{s}$ in duty cycle 2.5% and synchronization period 20 sec.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.14 no.2
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• pp.91-97
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• 2014

Chaotic dynamics is an active research area in fields such as biology, physics, sociology, psychology, physiology, and engineering. Interest in chaos is also expanding to the social sciences, such as politics, economics, and societal events prediction. Most people pursue happiness, both spiritual and physical in many cases. However, happiness is not easy to define, because people differ in how they perceive it. Happiness can exist in mind and body. Therefore, we need to be happy in both simultaneously to achieve optimal happiness. To do this, we need to synchronize mind and body. In this paper, we propose a chaotic synchronization method in a mathematical model of happiness organized by a second-order ordinary differential equation with external force. This proposed mathematical happiness equation is similar to Duffing's equation, because it is derived from that equation. We introduce synchronization method from our mathematical happiness model by using the derived Duffing equation. To achieve chaotic synchronization between the human mind and body, we apply an idea of mind/body unity originating in Oriental philosophy. Of many chaotic synchronization methods, we use only coupled synchronization, because this method is closest to representing mind/body unity. Typically, coupled synchronization can be applied only to non-autonomous systems, such as a modified Duffing system. We represent the result of synchronization using a differential time series mind/body model.

• Journal of Korea Multimedia Society
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• v.8 no.9
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• pp.1153-1162
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• 2005

In this paper, we developed an XML Document Data Synchronization System for java(XDS4j) based on both SyncML(Synchronization Markup Language) framework Sync4j and embedded database system Berkeley DB XML. Because most existing data synchronization systems are based on file systems, data synchronization times at Fast Sync in those systems are very delayed. In the XDS4j, however, XML documents data produced at SyncML client and SyncML server are managed by embedded database system, and also synchronization time at Fast Sync is reduced because only partial elements are accessed by applying to XPath.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.1
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• pp.38-46
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• 1992

In this thesis, a high speed code synchronization circuit is implemented, which is applicable to frequency hopping FSK tranceiver within 68-88 MIBz band- width. synchronization Process consists of two steps, initial synchronization and tracking. A modified matched filter method using two channel passive correlators matched with short hopping frequencies, synchronization prcfix. is proposed for initial synchronization. To increase probability of initial synchronization, prefix are transmitted repeatedly. The outputs of correlators are sent to synchronization decision circuit, and code start time Is extracted by synchronizatlon decision circuit-Modified matched fitter method makes it possible to reduce complexity in hardware and obtain code acquisition rapidly.Clock recovery circuit regenerates PN code clock for tracking.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.731-740
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• 2015

In the recent days, interests in machine-to-machine communication schemes in small-scale networks has been increasing with growing demands. TDMA(Time Division Multiple Access) can be used as a multiple access method in small-scale networks. However, time synchronization for TDMA is complicated or needs additional equipments. Such a large cost is not suitable for small-scale networks. We propose, BC-DESYNC, a efficient time synchronization for small-scale networks by extending DESYNC(DESYNChronization). DESYNC takes a long time to complete synchronization and doesn't guarantee the synchronization delay. BC-DESYNC uses CU(Central Unit) that performs a centralized control to achieve the 2-hop communication and guarantees the synchronization completion time by using Mimic firing and C-DESYNC scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1004-1009
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• 2004

Precise time synchronization is a main technology in high-speed communications, parallel and distributed processing systems, Internet information industry and electronic commerce. Synchronized clocks are useful for many leasers. Often a distributed system is designed to realize some synchronized behavior, especially in real-time processing in factories, aircraft, space vehicles, and military applications. Nowadays, time synchronization has been compulsory thing as distributed processing and network operations are generalized. A network time server obtains, keeps accurate and precise time by synchronizing its local clock to standard reference time source and distributes time information through standard time synchronization protocol. This paper describes design issues and implementation of a network time server for time synchronization especially based on a clock model. The system uses GPS (Global Positioning System) as a standard reference time source and offers UTC (universal Time coordinated) through NTP (Network Time protocol). Implementation result and performance analysis are also presented.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.216-223
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• 2005

A computer clock has limits in accuracy and precision affected by its inherent instability, the environment elements, the modification of users, and errors of the system. So the computer clock needs to be synchronized with a standard clock if the computer system requires the precise time processing. The purpose of synchronizing clocks is to provide a global time base throughout a distributed system. Once this time base exists, transactions among members of distributed system can be controlled based on time. This paper discusses the integrated approach to clock synchronization. An embedded system is considered for time synchronization based on the GPS(Global Positioning System) referenced time distribution model. The system uses GPS as standard reference time source and offers UTC(Universal Time Coordinated) through NTP(Network Time Protocol). A clock model is designed and adapted to keep stable time and to provide accurate standard time with precise resolution. Private MIB(Management Information Base) is defined for network management. Implementation results and performance analysis are also presented.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.1-10
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• 1994

In most application programs, loops usually contain most of the computation in a program and are the most improtant source of parallelism. When loops are executed on multiprocessors, the cross iteration data dependences need to be enforced by synchronization between processors. In this paper, we propose a new synchronization scheme(Free/Hold) for reducing overgeads occured by synchronization variables in data oriented scheme and delay of time occured by synchronization instruction in statement oriented scheme. The Free/Hold mechanism enforces the correct execution order by inserting synchronization instruction between each instance with data dependence relationship using the RD(Real dependence Distance). We also present an algorithm for removing unnecessary dependences in one-to-many dependences.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.522-525
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• 2007

Frame Synchronization is applied to not only digital data transmission for data synchronization between transmitter and receiver but also data communication with satellite. When satellite image data with high resolution and mass storage is transmitted, hardware frame synchronizer for real-time processing or software frame synchronizer for post-processing is used. In case of hardware, processing with high speed is available but data loss may happen for Search of Frame Synchronization. In case of software, data loss does not happen but speed is relatively slow. In this paper, Pending Buffer concept was proposed to cope with data loss according to processing status of Frame Synchronization. Algorithm to process Frame synchronization with high speed using bit threshold search algorithm with pattern search technique and SIMD is also proposed.