• Title/Summary/Keyword: Time Delay Error

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Observer Design for A Class of UncertainState-Delayed Nonlinear Systems

  • Lu Junwei;Feng Chunmei;Xu Shengyuan;Chu Yuming
    • International Journal of Control, Automation, and Systems
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    • v.4 no.4
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    • pp.448-455
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    • 2006
  • This paper deals with the observer design problem for a class of state-delayed nonlinear systems with or without time-varying norm-bounded parameter uncertainty. The nonlinearities under consideration are assumed to satisfy the global Lipschitz conditions and appear in both the state and measured output equations. The problem we address is the design of a nonlinear observer such that the resulting error system is globally asymptotically stable. For the case when there is no parameter uncertainty, a sufficient condition for the solvability of this problem is derived in terms of linear matrix inequalities and the explicit formula of a desired observer is given. Based on this, the robust observer design problem for the case when parameter uncertainties appear is considered and the solvability condition is also given. Both of the solvability conditions obtained in this paper are delay-dependent. A numerical example is provided to demonstrate the applicability of the proposed approach.

The Process Analysis and Application Methods for PLC Code Programming (PLC 코드 작성을 위한 공정 분석 및 적용 방법)

  • Koo, Lock-Jo;Yeo, Sung-Joo;Lee, Kang-Gu;Hong, Sang-Hyun;Park, Chang-Mok;Park, Sang-Chul;Wang, Gi-Nam
    • IE interfaces
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    • v.21 no.3
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    • pp.294-301
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    • 2008
  • Agile and flexible manufacturing systems make it mandatory that a control program should have features such as agility, flexibility, and reusability in order to run manufacturing unit smoothly. PLCs are the most frequently used control program in manufacturing systems. PLC programs are mostly programmed by subcontraction, which makes correction of code very difficult. As a result, it may cause delay during down time and ramp up time which leads to big loss of revenue and goodwill. To prevent delay during the times, this paper proposes systematic process analysis and application method for programmable logic controller like LLD (Ladder Logic Diagram). The proposed method uses modified human-error investing techniques for documentation and transforming technique to program LLD from the documentation. Furthermore, this paper demonstrates an example of piston mechanism to explain the proposed method.

Transparency Implementation for Bilateral Teleoperation System by using Two-channel Control Architecture (2채널 제어 구조를 사용한 양방향 원격조종 시스템의 투명도 구현)

  • Kim, Jong-Hyun;Chang, Pyung-Hun;Park, Hyung-Soon
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.27 no.11
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    • pp.1967-1978
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    • 2003
  • Transparency has been considered as a performance measure in bilateral teleoperation system. Therefore, many issues of transparency have been studied. This paper investigates the transparency in two-channel control architectures. At first, we show the feasibility using analytic transparency-conditions and present the two classes of two-channel control architecture, which are perfectly transparent under ideal situation. In addition, remedies to problems due to impedance model estimation errors under real situation are introduced. They are as fellows; design guideline of control parameters to reduce the effect of model estimation error effect and introduction of time delay estimation for unknown dynamics. From these analyses, the systematic control scheme, which is stable and well transparent under real implementation, is proposed in two-channel control architecture. Finally, the proposed scheme is applied to a 2 D.O.F master-slave system and the experimental results show the validity of the theoretical work.

A Study on Response Time Delay and Tracking Error Suppression Strategy in Gear Mechanism : Control System Design Approach (기어 백래쉬로 인한 응답지연 및 추종오차 억제방안에 관한 연구)

  • Tran, Manh Son;Choi, Eun-Ho;KIM, Young-Bok
    • Journal of Power System Engineering
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    • v.21 no.4
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    • pp.77-83
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    • 2017
  • The aim of this paper is to solve the chattering and delayed response problems caused by gear backlash. In the gear mechanism based systems, for example, in robot systems, the actuators provide the reduction gear with motors to transfer effectively electric power to mechanical power. Therefore, the gear backlash exists and is an unavoidable fact which makes many undesirable problems. In this paper, the authors try to make a solution for this issue and, introduce several control methods which are PID only, PID with Smith predictor and super-twisting algorithm based SMC(sliding mode control). Each control method is applied to the real plant in which strong backlash is included. By comparison results, it is clear that SMC gives the best control performance with little backlash effects. Also, the usefulness and effectiveness of proposed control method is verified by experiment.

Quality Assessment of Tropospheric Delay Estimated by Precise Point Positioning in the Korean Peninsula

  • Park, Han-Earl;Roh, Kyoung Min;Yoo, Sung-Moon;Choi, Byung-Kyu;Chung, Jong-Kyun;Cho, Jungho
    • Journal of Positioning, Navigation, and Timing
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    • v.3 no.4
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    • pp.131-141
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    • 2014
  • Over the last decade, the Global Navigation Satellite System (GNSS) has been increasingly utilized as a meteorological research tool. The Korea Astronomy and Space Science Institute (KASI) has also been developing a near real-time GNSS precipitable water vapor (PWV) information management system that can produce a precise PWV for the Korean Peninsula region using GNSS data processing and meteorological measurements. The goal of this paper is to evaluate whether the precise point positioning (PPP) strategy will be used as the new data processing strategy of the GNSS-PWV information management system. For this purpose, quality assessment has been performed by means of a comparative analysis of the troposphere zenith total delay (ZTD) estimates from KASI PPP solutions (KPS), KASI network solutions (KNS), and International GNSS Service (IGS) final troposphere products (IFTP) for ten permanent GNSS stations in the Korean Peninsula. The assessment consists largely of two steps: First, the troposphere ZTD of the KNS are compared to those of the IFTP for only DAEJ and SUWN, in which the IFTP are used as the reference. Second, the KPS are compared to the KNS for all ten GNSS stations. In this step, the KNS are used as a new reference rather than the IFTP, because it was proved in the previous step that the KNS can be a suitable reference. As a result, it was found that the ZTD values from both the KPS and the KNS followed the same overall pattern, with an RMS of 5.36 mm. When the average RMS was converted into an error of GNSS-PWV by considering the typical ratio of zenith wet delay and PWV, the GNSS-PWV error met the requirement for PWV accuracy in this application. Therefore, the PPP strategy can be used as a new data processing strategy in the near real-time GNSS-PWV information management system.

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

  • Yoo, Byoung-Joo;Song, Ho-Young;Chi, Han-Kyu;Bae, Woo-Rham;Jeong, Deog-Kyoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.4
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    • pp.433-448
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    • 2012
  • A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

SACK-SNOOP Protocol for Wireless TCP Performance Improvement (무선 TCP 성능 향상을 위한 SACK-SNOOP 프로토콜)

  • Ahn, Chi-Hyun;Kim, Hyung-Chul;Woo, Jong-Jung;Kim, Jang-Hyung;Lee, Dae-Young;Jun, Kye-Suk
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.2
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    • pp.392-401
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    • 2007
  • Wireless network has high BER characteristic because of path loss, fading, noise and interference. Many packet losses occur without any congestion in wireless network. Therefore, many wireless TCP algorithms have been proposed. SNOOP, one of wireless TCP algorithms, hides packet losses for Fixed Host and retransmits lost packets in wireless network. However, SNOOP has a weakness for bust errors in wireless network. This paper proposes the SACK-SNOOP to improve TCP performance based on SNOOP and Freeze-TCP that use ZWA messages in wireless network. This message makes FH stop sending packets to MH. BS could retransmit error packets to MH for this time. SACK-SNOOP use improved Selective ACK, thereby reducing the number of packet sequences according to error environment. This method reduces the processing time for generation, transmission, analysis of ACK. This time gain is enough to retransmit local burst errors in wireless link. Furthermore, SACK-SNOOP can manage the retransmitted error by extending delay time to FH. The simulation shows that our proposed protocol is more effective for packet losses in wireless networks.

Wide Range Analog Dual-Loop Delay-Locked Loop (광대역 아날로그 이중 루프 Delay-Locked Loop)

  • Lee, Seok-Ho;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.1
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    • pp.74-84
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    • 2007
  • This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

Precision Time Synchronization System over Wireless Networks for TDOA-based Real Time Locating Systems (TDOA 기반의 실시간 위치 측정 시스템을 위한 정밀 무선 시각 동기 시스템)

  • Cho, Hyun-Tae;Jung, Yeon-Su;Jang, Hyun-Sung;Park, In-Gu;Baek, Yun-Ju
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.1B
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    • pp.86-97
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    • 2009
  • RTLS is a system for automatically locating and tracking people and objects. The TDOA-based RTLS determines the location of the tag by calculating the time differences of a signal received from the tag. In TDOA-based RTLS, time synchronization is essential to calculate the time difference between readers. This paper presents a precision time synchronization method for TDOA-based RTLS over IEEE 802.15.4. In order to achieve precision time synchronization in IEEE 802.15.4 radio, we analyzed the error factors of delay and jitter. We also deal with the implementation of hardware assisted time stamping and the Kalman filtering method to minimize the error factors. In addition, this paper described the experiments and performance evaluation of the proposed precision time synchronization method in IEEE 802.15.4 radio. The results show that the nodes in a network can maintain their clocks to within 10 nanoseconds offset from the reference clock.

Comparison of PID Controller Tuning of Power Plant Using Immune and Genetic Algorithms

  • Kim, Dong-Hwa
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2003.09a
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    • pp.358-363
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    • 2003
  • Optimal tuning plays an important role in operations or tuning of the complex process such as the main steam temperature of the thermal power plant. However, it is very difficult to maintain the steam temperature of power plant using conventional optimization methods, since these processes have the time delay and the change of the dynamic characteristics in the reheater. Up to the present time, the Pm controller has been used. However, it is not easy to achieve an optimal PID gain with no experience, since the gain of the PID controller has to be manually tuned by trial and error. This paper suggests immune algorithm based tuning technique for PID Controller on steam temperature process with long dead time and its results are compared with genetic algorithm based tuning technique.

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