• Journal of the Korean Operations Research and Management Science Society
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• v.30 no.1
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• pp.149-159
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• 2005

In this study, we consider characteristics of stationary waiting times in single-server 2-node tandem queues with a finite buffer, a Poisson arrival process and deterministic service times. The system has two buffers: one at the first node is infinite and the other one at the second node is finite. We show that the sojourn time or departure process does not depend on the capacity of the finite buffer and on the order of nodes (service times), which are the same as the previous results. Furthermore, the explicit expressions of waiting times at the first node are given as a function of the capacity of the finite buffer and we are able to disclose a relationship of waiting times between under communication blocking and under manufacturing blocking. Some numerical examples are also given.

• Electrical & Electronic Materials
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• v.8 no.2
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• pp.204-210
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• 1995

The characteristics of the internal circuits and the load capacitance should be included to optimize the size of BiCMOS buffer. In order to get the optimum size and delay time of the BiCMOS buffer, new size plane is suggested. By using the size plane, the optimum characteristics of CMOS buffer according to the number of stages can be obtained. From this method, delaytime, .tau.$_{D}$, is obtained 2.39 nsec with $V_{\var}$=5V, $C_{L}$=5pF, W=30.mu.m and $A_{e}$=135.mu. $m^{2}$.>..>...>.

• Korean Management Science Review
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• v.24 no.1
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• pp.25-34
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• 2007

In this study, we consider stationary waiting times in finite-buffer 3-node single-server queues in series with a Poisson arrival process and with either constant or non-overlapping service times. We assume that each node has a finite buffer except for the first node. The explicit expressions of waiting times in all areas of the stochastic system were driven as functions of finite buffer capacities. These explicit forms show that a system sojourn time does not depend on the finite buffer sizes, and also allow one to compute and compare characteristics of stationary waiting times at all areas under two blocking rules communication and manufacturing blocking. The goal of this study is to apply these results to an optimization problem which determines the smallest buffer capacities satisfying predetermined probabilistic constraints on stationary waiting times at all nodes. Numerical examples are also provided.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.28-35
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• 1997

A new approach concurrent transistor sizing and buffer insertion for low power optimization is proposed in this paper. The method considers the tradeoff between upsizing transistors and inserting buffers and chooses the solution with the lowest possible power and area cost. It operates by analyzing the feasible region of the cost-delay curves of the unbuffered and buffered circuits. As such the feasible region of circuits optimized by our method is extended to encompass the envelop of cost-delay curves which represent the union of the feasible regions of all buffered ad unbuffered versions of the circuit. The method is efficient and tunable in that optimality can be traded for compute time and as a result it can in theory near optimal results.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.167-176
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• 2012

In this paper we design and implement a new Hybrid Equipment Data Acquisition System (HEDAS) for data collection of semiconductor and optoelectronic manufacturing equipments in the equipment engineering system(EES) framework. The amount of the data collected from equipments have increased rapidly in equipment engineering system. The proposed HEDAS efficiently handles a large amount of real-time equipment data generated from EES framework. It also can support the real-time ESS applications as well as non real-time ESS applications. For the real-time EES applications, it performs high-speed real-time processing that uses continuous query and filtering techniques based on memory buffers. The HEDAS can optionally store non real-time equipment data using a HEDAS-based database or a traditional DBMS-based database. In particular, The proposed HEDAS offers the compression indexing based on the timestamp of data and query processing technique saving the cost of disks storage against extremely increasing equipment data. The HEDAS is efficient system to collect huge real-time and non real-time equipment data and transmit the collected equipment data to several EES applications in EES framework.

• Journal of Korea Multimedia Society
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• v.2 no.1
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• pp.59-68
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• 1999

Multimedia applications have an ability to transmit a lot of data in real time. In mobile circumstances the replay of continuous multimedia data in real time causes frequent replay breaks and poor service quality because of low transmission speed and new transmission path settings in hand-off. To avoid these unfavorable side effects, we need a new mechanism which can transmit data efficiently between base station and mobile hosts, to control the buffers of mobile hosts, and to switch to a new transmission path rapidly in hand-off. The study is to propose how to give good service to mobile hosts during hand-off and the mechanism which can increase the number of mobile hosts in the cell unit.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.51-58
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• 2010

This paper proposes an edge adaptive color interpolation for an ultra-small HD-grade complementary metal-oxide semiconductor (CMOS) video sensor in camera phones that can process 720-p/30-fps videos. Recently, proposed methods with great image quality perceptually reconstruct the green component and then estimate the red/blue component using the reconstructed green and neighbor red and blue pixels. However, these methods require the bulky memory line buffers in order to temporally store the reconstructed green components. The edge adaptive color interpolation method uses seven or nine patterns to calculate the six edge directions. At the same time, the threshold values are adaptively adjusted by the sum of the color values of the selected pixels. This method selects the suitable one among the patterns using two flowcharts proposed in this paper, and then interpolates the missing color values. For verification, we calculated the peak-signal-to-noise-ratio (PSNR) in the test images, which were processed by the proposed algorithm, and compared the calculated PSNR of the existing methods. The proposed color interpolation is also fabricated with the 0.18-${\mu}m$ CMOS flash memory process.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• ETRI Journal
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• v.38 no.5
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• pp.847-857
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• 2016

Broadcasting services such as multi/single channel HDTV and 3DTV/2DTV use a multi-channel encoder that changes the bitrate and composition of the video service depending on the time. However, this type of multi-channel encoder could cause a longer latency owing to the variable bitrate and relatively bigger size of the buffers, which results in the same delay as in 3DTV even for a conventional DTV service. On the other hand, systems built based on separate encoders, each of which is optimized for the target service, might not have such latency problems. Nevertheless, there might be a distortion problem in the image and sound at the time of a switchover between two encoders with different output bitrates and group of picture structures. This paper proposes a system that can realize a seamless video service conversion using two different video encoders optimized for each video service. An overall functional description of the video service change control server, which is a main control block for the proposed system, is also provided. The experiment results confirm the seamless switchover and reduced broadcasting latency of DTV services compared with a broadcasting system composed of a multi-channel encoder system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.157-169
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• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.