• 정보저장시스템학회:학술대회논문집
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• 정보저장시스템학회 2005년도 추계학술대회 논문집
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• pp.124-127
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• 2005

Rewritable optical memory devices such as an CD-RW and DVD+RW are data storage media, which take advantage of the different optical properties in the amorphous and crystalline states of phase change materials. The switching property, structural transformation, transformation kinetics and chemical bindings of $Ge_xSb_{100-x}$($6{\le}x{\le}$34) were studied to investigate the feasibility of applying $Ge_xSb_{100-x}$ alloys in optical memory. The $Ge_xSb_{100-x}$ thin film was deposited by RF magnetron co-sputtering system and phase change characteristics were investigated by X-ray diffraction (XRD), static tester, inductively coupled plasma atomic emission spectrometer (ICP-AES) and atomic force microscopy (AEM). Optimum fiim composition of $Ge_xSb_{100-x}$ was studied and its minimum time fur laser induced crystallization and optical contrast fur phase transition was performed. These results might be correlated with the binding energies between Ge and Sb, and indicate that $Ge_xSb_{100-x}$ have an potential far optical memory applications.

• 한국전기전자재료학회논문지
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• 제15권5호
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• pp.449-454
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• 2002

The use of a thin film of indium between the ITO and the $n^+-lnP$ contact layers for InP/InGaAs HPTs was studied without degrading its excellent optical transmittance properties. $ITO/n^+-lnP$ ohmic contact was successfully achieved by the deposition of indium and annealing. The specific contact resistance of about $6.6{\times}10^{-4}\Omega\textrm{cm}^2$ was measured by use of the transmission line method (TLM). However, as the thermal annealing was just performed to $ITO/n^+-lnP$ contact without the deposition of indium between ITO and $n^+-lnP$, it exhibited Schottky characteristics. In the applications, the DC characteristics of InP/InGaAs HPTs with ITO emitter contacts was compared with those of InP/InGaAs HBTs with the opaque emitter contacts.

• 한국결정학회:학술대회논문집
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• 한국결정학회 2002년도 정기총회 및 추계학술연구발표회
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• pp.48-48
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• 2002

It is generally accepted that ultra low dielectric interlayer dielectric materials (k < 2.2) will be necessary for ULSI advanced microelectronic devices after 2003, according to the International Technology Roadmap for Semiconductors (ITRS) 2000. A continuous reduction of dielectric constant is believed to be possible only by incorporating nanopores filled with air (k = 1.0) into electrically insulating matrices such as poly(methyl silsesquioxane) (PMSSQ). The nanopo.ous low dielectric films should have excellent material properties to survive severe mechanical stress conditions imposed during the advanced semiconductor processes such as chemical mechanical planarization process and multilayer fabrication. When air is incorporated into the films for lowering k, their mechanical strength has inevitably to be sacrificed. To minimize this effect, the nanopores are controlled to exist in the film as closed cells. The micromechanical properties of the nanoporous thin films are considered more seriously than ever, particularly for ultra low dielectric applications. In this study, three approaches were made to design and develop nanoporous low dielectric films with improved micromechanical properties: 1) wall density increase of nanoporous organosilicate film by copolymerization of carbon bridged comonomers; 2) incorporation of sacrificial phases with good miscibility; 3) selective surface modification by plasma treatment. Nanoporous low-k films were prepared with copolymerized PMSSQ and star-shaped sacrificial organic molecules, both of which were synthesized to control molecular weight and functionality. The nanoporous structures of the films were observed using field emission scanning electron microscopy, cross-sectional transmission electron microscopy, atomic force microscopy, and positronium annihilation lifetime spectroscopy(PALS). Micromechanical characterization was performed using a nanoindentor to measure hardness and modulus of the films.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.176-176
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• 2010

One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio (Ion/Ioff), leakage current, threshold voltage, and hysteresis under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stability of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers was investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic-layer-deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to 105 times with 5mm bending radius. In the most of the devices after 105 times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the Ion/Ioff and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.31.1-31.1
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• 2009

Carbon nanotubes (CNTs) are attractive material because of their superior electrical, mechanical, and chemical properties. Furthermore, their geometric features such as a large aspect ratio and a small radius of curvature at tip make them ideal for low-voltage field emission devices including backlight units of liquid crystal display, lighting lamps, X-ray source, microwave amplifiers, electron microscopes, etc. In field emission devices for display applications, the phosphor anode is positioned against the CNT emitters. In most case, light generated from the phosphor by electron bombardment passes through the anode front plate to reach observers. However, light is produced in a narrow depth of the surface of the phosphor layer because phosphor particles are big as much as several micrometers, which means that it is necessary to transmit through the phosphor layer. Hence, a drop of light intensity is unavoidable during this process. In this study, we fabricated a transparent cathode back plate by depositing an ultra-thin film of single walled CNTs (SWCNTs) on an indium tin oxide (ITO)-coated glass substrate. Two types of phosphor anode plates were employed to our transparent cathode back plate: One is an ITO glass substrate with a phosphor layer and the other is a Cr-coated glass substrate with phosphor layer. For the former case, light was radiated from both the front and the back sides, where luminance on the back was ~30% higher than that on the front in our experiments. For the other case, however, light was emitted only from the cathode back side as the Cr layer on the anode glass rolled as a reflecting mirror, improving the light luminance as much as ~60% compared with that on the front of one. This study seems to be discussed about the morphologies and field emission characteristics of CNT emitters according to the experimental parameters in fabricating the lamps emitting light on the both sides or only on the cathode back side. The experimental procedures are as follows. First, a CNT aqueous solution was prepared by ultrasonically dispersing purified SWCNTs in deionized water with sodium dodecyl sulfate (SDS). A milliliter or even several tens of micro-liters of CNT solution was deposited onto a porous alumina membrane through vacuum filtration. Thereafter, the alumina membrane was solvated with the 3 M NaOH solution and the floating CNT film was easily transferred to an ITO glass substrate. It is required for CNT film to make standing CNTs up to serve as electron emitter through an adhesive roller activation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.65-65
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• 2007

Microstructure and surface roughness of the sensing materials should be improved to use them in advanced sensor applications because the uneven surface roughness degrades the light reflection, pattern resolution, and devices performance. Chemical mechanical polishing (CMP) processing was selected for improving the surface roughness of $CeO_2$ which is one of the well known materials for the oxygen gas sensors. Surface roughness and removal rate of spin coated $CeO_2$ thin films were examined with a change of CMP process parameters such as down force and table speed. The optimized process condition, reflected by the surface roughness with the hillock-free surface as well as the excellent removal rate with the good uniformity, was obtained. The effects of the improved surface roughness on the sensing property of $CeO_2$ thin films were also confirmed. The improved sensitivity of $CeO_2$ thin films for oxygen sensors were obtained after CMP process by the improved surface characteristics. Therefore, we conclude that sensing property of $CeO_2$ thin film is strongly dependent on the surface roughness of $CeO_2$ thin films by using CMP process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.327.1-327.1
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• 2014

Nitrides-on-silicon structures are considered to be an excellent candidate for unique design architectures and creating devices for high-power applications. Therefore, a lot of effort has been concentrating on growing high-quality III-nitrides on Si substrates, mostly Si(111) and Si(001) substrates. However, there are several fundamental problems in the growth of nitride compound semiconductors on silicon. First, the large difference in lattice constants and thermal expansion coefficients will lead to misfit dislocation and stress in the epitaxial films. Second, the growth of polar compounds on a non-polar substrate can lead to antiphase domains or other defective structures. Even though the lattice mismatches are reached to 16.9 % to GaN and 19 % to AlN and a number of dislocations are originated, Si(111) has been selected as the substrate for the epitaxial growth of nitrides because it is always favored due to its three-fold symmetry at the surface, which gives a good rotational matching for the six-fold symmetry of the wurtzite structure of nitrides. Also, Si(001) has been used for the growth of nitrides due to a possible integration of nitride devices with silicon technology despite a four-fold symmetry and a surface reconstruction. Moreover, Si(110), one of surface orientations used in the silicon technology, begins to attract attention as a substrate for the epitaxial growth of nitrides due to an interesting interface structure. In this system, the close lattice match along the [-1100]AlN/[001]Si direction promotes the faster growth along a particular crystal orientation. However, there are insufficient until now on the studies for the growth of nitride compound semiconductors on Si(110) substrate from a microstructural point of view. In this work, the microstructural properties of nitride thin layers grown on Si(110) have been characterized using various TEM techniques. The main purpose of this study was to understand the atomic structure and the strain behavior of III-nitrides grown on Si(110) substrate by molecular beam epitaxy (MBE). Insight gained at the microscopic level regarding how thin layer grows at the interface is essential for the growth of high quality thin films for various applications.

• 한국재료학회지
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• 제12권6호
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• pp.464-469
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• 2002

$SrBi_2Nb_2O_9(SBN)$ thin films were grown on Pt/Ti/Si and p-type Si(100) substrates by rf-magnetron co-sputtering method using two ceramic targets, $SrNb_2O_6\; and \;Bi_2O_3$. The structural and electrical characteristics have been investigated to confirm the possibility of the SBN thin films for the applications to destructive and nondestructive read out ferroelectric random access memory(FRAM). For the optimum growth condition X-ray diffraction patterns showed that SBN films had well crystallized Bi-layered perovskite structure after $700^{\circ}C$ heat-treatment in furnace. From this specimen we got remnant polarization $(2P_r)$ of about 6 uC/$\textrm{cm}^2$ and coercive voltage $(V_c)$ of about 1.5 V at an applied voltage of 5 V. The leakage current density was $7.6{\times}10^{-7}$/A/$\textrm{cm}^2$ at an applied voltage of 5V. And for the NDRO-FRAM application, properties of SBN films on Si substrate has been investigated. From transmission electron microscopy (TEM) analysis, we found the furnace treated sample had a native oxide about 2 times thicker than the RTA treated sample and this thick native oxide layer had a bad effect on C-V characteristics of SBN/Si thin film. After $650^{\circ}C$ RTA process, we got the improved memory window of 1.3 V at an applied voltage of 5 V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.