• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.396-396
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• 2007

Highly ordered pore structures as a template for formation of seeds have been prepared by the self-organization process of aluminum oxidation. The a-Si films were deposited on the anodic alumina films and crystallized by laser irradiation. It was found that un-melted part of fine poly-Si grain formed by explosive crystallization (EX) lead super lateral growth(SLG) and occluded with neighbor grains. The crystallized grains along the distribution of seeds were obtained. This results show a great potential for use in novel crystallization for decently uniform polycrystalline Si thin film transistors (poly-Si TFTs).

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.434-435
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• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.33-39
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• 2015

In this work, SU-8 passivated IZO thin-film transistors(TFTs) made by solution-processes was investigated for enhancing stability of indium zinc oxide(IZO) TFT. A very viscous negative photoresist SU-8, which has high mechanical and chemical stability, was deposited by spin coating and patterned on top of TFT by photo lithography. To investigate the enhanced electrical performances by using SU-8 passivation layer, the TFT devices were analyzed by X-ray phtoelectron spectroscopy(XPS) and Fourier transform infrared spectroscopy(FTIR). The TFTs with SU-8 passivation layer show good electrical characterestics, such as ${\mu}_{FE}=6.43cm^2/V{\cdot}s$, $V_{th}=7.1V$, $I_{on/off}=10^6$, SS=0.88V/dec, and especially 3.6V of ${\Delta}V_{th}$ under positive bias stress (PBS) for 3600s. On the other hand, without SU-8 passivation, ${\Delta}V_{th}$ was 7.7V. XPS and FTIR analyses results showed that SU-8 passivation layer prevents the oxygen desorption/adsorption processes significantly, and this feature makes the effectiveness of SU-8 passivation layer for PBS.

• Bulletin of the Korean Chemical Society
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• v.33 no.2
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• pp.541-548
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• 2012

New candidates composed of anthracene and 4-alkylethynylbenzene end-capped oligomers for OTFTs were synthesized under Sonogashira coupling reaction conditions. All oligomers were characterized by FT-IR, mass, UV-visible, and PL emission spectrum analyses, cyclic voltammetry (CV), differential scanning calorimetry (DSC), thermal gravimetric analysis (TGA), $^1H$-NMR, and $^{13}C$-NMR. Investigation of their physical properties showed that the oligomers had high oxidation potential and thermal stability. Thin films of DHPEAnt and DDPEAnt were characterized by spin coating them onto Si/$SiO_2$ to fabricate top-contact OTFTs. The devices prepared using DHPEAnt and DDPEAnt showed hole field-effect mobilities of $4.0{\times}10^{-3}cm^2$/Vs and $2.0{\times}10^{-3}cm^2$/Vs, respectively, for solution-processed OTFTs.

• Journal of the Korean Vacuum Society
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• v.20 no.2
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• pp.77-85
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• 2011

The silicon-germanium (SiGe) alloy, which is compatible with silicon semiconductor technology and has a smaller band gap and a lower thermal conductivity than silicon, has been used to fabricate electronic devices such as transistors, photodetectors, solar cells, and thermoelectric devices. This paper reviews the application of SiGe alloys to electronic devices and related technical issues. Since the SiGe alloy comprises germanium whose band gap is smaller than silicon, its band gap is also smaller than that of silicon irrespective of the ratio of silicon to germanium. This narrow band gap of SiGe enables the base thickness of bipolar transistors to decrease without a loss in current gain so that it is possible to improve the speed of bipolar transistors by adopting the SiGe-base. In addition, the conversion efficiency of solar cells is enhanced by the absorption of long-wavelength light in the SiGe absorption layer. Phonon scattering caused by the irregular distribution of alloying elements induces the lower thermal conductivity of SiGe than those of pure silicon and germanium. Because a thin film layer with a low thermal conductivity suppresses thermal conduction through a thermal sink, the SiGe alloy is considered to be a promising material for silicon-based thermoelectric systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.344-349
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• 2006

The low-temperature processing is very important for fabrication of the very large scale ($60{\sim}70nm$) semiconductor devices since the submicron transistors are sensitive to the thermal budget. Hence, in this work, we propose a noble low-temperature LPCVD (Low-Pressure Chemical Vapor Deposition) process for the $SiO_2$ film and evaluate the electrical reliability of the LTO (Low-Temperature Oxide) by making the capacitors with ONO (Oxide/Nitride/Oxide) structure. The leak current of the LTO was similar to that of the high-temperature wet oxide until the electric field was lower than 5 MV/cm. However, when the electric field was higher, the LTO showed much better characteristics.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.348-348
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• 2014

차세대 디스플레이 구동 회로 소자를 위한 재료로서, Amorphous Oxide Semiconductor (AOS)가 주목받고 있다. AOS는 기존의 Amorphous Silicon과 비교하여 뛰어난 이동도를 가지고 있으며, 넓은 밴드 갭에 의한 투명한 광학적 특성을 가지고 있다. 이러한 장점을 이용하여, AOS 박막은 thin film transistor (TFT)의 active channel로 이용 되고 있다. 하지만, AOS를 이용한 TFT의 경우, 시간이 경과함에 따라 $O_2$ 및 $H_2O$ 흡착에 의해 전기적 특성이 변하는 현상이 있다. 이러한 현상은 소자의 신뢰성에 있어 중요한 문제가 된다. 이러한 문제를 연구하기 위해 본 논문에서는, AOS 박막을 이용하여 bottom 게이트형 TFT를 제작하였다. 이를 위해 먼저, p-type Si 위에 건식산화방식으로 $SiO_2$(100 nm)를 성장시켜 게이트 산화막으로 이용하였다. 그리고 Zn과 Sn이 1: 2의 조성비를 가진 ZnSnO (ZTO) 용액을 제조한 후, 게이트 산화막 위에 spin coating 하였다. Splin coating된 용액에 남아 있는 솔벤트를 제거하기 위해 10분 동안 $230^{\circ}C$로 열처리를 한 후, 포토리소그래피와 에칭 공정을 이용하여 ZTO active channel을 형성하였다. 그 후, 박막 내에 남아 있는 불순물을 제거하고 ZTO TFT의 전기적인 특성을 향상시키기 위하여, $600^{\circ}C$의 열처리를 30분 동안 진행 하여 junctionless형 TFT 제작을 완료 하였다. 제작된 소자의 시간 경과에 따른 열화를 확인하기 위하여, 대기 중에서 2시간마다 HP-4156B 장비를 이용하여 전기적인 특성을 확인 하였으며, 이러한 열화는 후처리 공정을 통하여 회복시킬 수 있었다. 열화의 회복을 위한 후처리 공정으로, 퍼니스를 이용한 고온에서의 열처리와 microwave를 이용하여 저온 처리를 이용하였다. 결과적으로, TFT는 소자가 제작된 이후, 시간에 경과함에 따라서 on/off ratio가 감소하여 열화되는 경향을 보여 주었다. 이러한 현상은, TFT 소자의 ZTO back-channel에 대기 중에 있는 $O_2$ 및 $H_2O$의 분자의 물리적인 흡착으로 인한 것으로 보인다. 그리고 추가적인 후처리 공정들에 통해서, 다시 on/off ratio가 회복 되는 현상을 확인 하였다. 이러한 추가적인 후처리 공정은, 열화된 소자에 퍼니스에 의한 고온에서의 장시간 열처리, microwave를 이용한 저온에서 장시간 열처리, 그리고 microwave를 이용한 저온에서의 단 시간 처리를 수행 하였으며, 모든 소자에서 성공적으로 열화 되었던 전기적 특성이 회복됨을 확인 할 수 있었다. 이러한 결과는, 저온임에도 불구하고, microwave를 이용함으로 인하여, 물리적으로 흡착된 $O_2$ 및 $H_2O$가 짧은 시간 안에 ZTO TFT의 back-channel로부터 탈착이 가능함과 동시에 소자의 특성을 회복 가능 함 의미한다.