• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.444-444
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• 2011

Recently, patterned magnetic films and elements attract a wide interest due to their technological potentials in ultrahigh-density magnetic recording and spintronic devices. Among those patterned magnetic structures, magnetic anti-dot patterning induces a strong shape anisotropy in the film, which can control the magnetic properties such as coercivity, permeability, magnetization reversal process, and magneto-resistance. While majority of the previous works have been concentrated on anti-dot arrays with a single magnetic layer, there has been little work on multilayered anti-dot arrays. In this work, we report on study of the magnetic properties of bilayered anti-dot system consisting of upper perforated Co layer of 40 nm and lower continuous Ni layer of 5 nm thick, fabricated by photolithography and wet-etching processes. The magnetic hysteresis (M-H) loops were measured with a superconducting-quantum-interference-device (SQUID) magnetometer (Quantum Design: MPMS). For comparison, investigations on continuous Co thin film and single-layer Co anti-dot arrays were also performed. The magnetic-domain configuration has been measured by using a magnetic force microscope (PSIA: XE-100) equipped with magnetic tips (Nanosensors). An external electromagnet was employed while obtaining the MFM images. The MFM images revealed well-defined periodic domain networks which arise owing to the anisotropies such as magnetic uniaxial anisotropy, configurational anisotropy, etc. The inclusion of holes in a uniform magnetic film and the insertion of a uniform thin Ni layer, drastically affected the coercivity as compared with single Co anti-dot array, without severely affecting the saturation magnetization ($M_s$). The observed changes in the magnetic properties are closely related to the patterning that hinders the domain-wall motion as well as to the magneto-anisotropic bilayer structure.

• 한국자기학회지
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• 제16권1호
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• pp.75-78
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• 2006

텅스턴-보론-카본질소 화합물 박막(W-B-C-N)을 만들기 위하여 박막내에 보론과 카본 그리고 질소의 불순물을 주입한 다음 결정구조를 조사하였으며, 이러한 박막의 식각 특성을 조사하기 위하여 고온에서 열처리한 다음 Cu박막을 W-B-C-N 박막위에 증착한 다음에 열처리하였고 여기에서 열적인 특성을 조사하였다. $1000\;{\AA}$의 박막을 RF magnetron sputtering방법을 이용하여 증착한 후에 박막의 전기적구조적인 특성을 측정하였으며, scratch test를 통해 박막의 결합력을 측정하였고, XRD측정을 통하여 결정성을 조사하였으며, 열처리한 후 etching을 하여 nomarski 현미경을 통하여 확산방지막의 안정성을 조사하였다. 이로부터 확산방지막내의 보론과 카본 질소 등의 불순물이 들어감에 따라 Cu가 Si 속으로 얼마나 들어가는가를 효과적으로 조사하였다. W-B-C-N 확산방지막의 역할은 $850^{\circ}C$까지 고온 열처리를 하는 경우에 Cu 원자가 Si 속으로 확산되어 나가는 것을 효과적으로 방지하는 것을 알 수 있었다. 텅스텐-보론-카본질소 화합물 박막의 비저항은 질소 가스의 유량비를 조절함으로써 쉽게 조절할 수 있었으며, 텅스텐-보론-카본-질소 화합물 박막은 Cu 확산방지막으로 적용했을 때 적절한 질소 농도가 들어간 확산방지막에서는 효과적으로 Cu의 확산을 방지하는 것을 알 수 있었다.

• Journal of Electrochemical Science and Technology
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• 제8권1호
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• pp.15-24
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• 2017

A comparative study was performed on the passivating abilities of surface films generated on lithium titanate (LTO; $Li_4Ti_5O_{12}$) electrodes during pre-cycling at two different rates. The surface film deposited at a faster pre-cycling rate (i.e., 0.5 C) is irregularly shaped and unevenly covers the LTO electrode. Owing to the incomplete coverage of the protective film, this LTO electrode exhibits poor passivating ability. Additional electrolyte decomposition and concomitant film deposition occur during subsequent charge/discharge cycles. As a result of the thick surface film, severe cell polarization occurs and eventually causes cell failure. However, pre-cycling the Li/LTO cell at a slower rate (0.1 C) improves cell polarization and capacity retention; this occurs because the surface film uniformly covers the LTO electrode and provides strong passivation. Accordingly, there is no significant film deposition during subsequent charge/discharge cycling. Additionally, self-discharge is reduced during high-temperature storage.

• 한국자기학회지
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• 제9권2호
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• pp.104-110
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• 1999

조성, 열처리 및 강자성 상하지층이 AgCo 나노입상 합금박막의 거대자기저항과 포화자기장에 미치는 효과에 대하여 연구하였다. 합금박막의 두께가 50nm이하에서는 두께가 감소함에 따라 자기저항이 급격히 감소하고 포화자기장은 증가한다. 합금박막의 Co조성의 증가, 열처리 및 Fe 상하지층의 피복으로 Co입자의 크기 및 밀도의 증가, 표면에서의 스핀전도산란의 감소로 합금박막 두께 감소에 따른 비저항차의 감소 및 포화자기장의 증가를 억제할 수 있었다. 합금박막의 Co조성이 30at.%이고 Fe(30nm)/AgCo(20nm)/Fe(30nm)인 삼층박막의 증착된 상태에서 포화자기장이 약5kOe, 자기저항값이 약 5%이었다. 합금박막의 Co 조성을 40at.%로 증가시키고 30$0^{\circ}C$에서 10분간 열처리한 경우 포화자기장은 약1kOe로 1/5로 줄었으나 자기저항 값은 5.16%로 변화가 없었다.

• 한국세라믹학회지
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• 제39권4호
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• pp.377-385
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• 2002

Metal-Ferroelectric-Insulator-Semiconductor(MFIS) 구조의 적용하기 위해 R. F. 마그네트론 스퍼터를 이용하여 p-type Si(111) 기판 위에 $ZrO_2$와 $SrBi_2Ta_2O_9$ 박막을 증착하였다. SBT 박막은 $ZrO_2$ 완충층을 삽입함으로써 MFIS 구조의 전기적인 특성이 향상되었다. $ZrO_2$ 박막의 두께를 고정하고 SBT 박막의 두께를 160nm에서 220nm으로 변화시키면서 윈도우 메모리를 3-9V의 범위에서 측정하였다. Pt/SBT(160nm)/$ZrO_2$(20nm)/Si의 조건에서 최대 2.2V 메모리 윈도우 값을 얻을 수 있었으며 이 메모리 윈도우 값은 실제 적용되는 저전압 NDRO-FRAM 구동에 충분한 값이다.

• 한국전기전자재료학회논문지
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• 제30권8호
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• pp.469-473
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• 2017

We investigated the effect of different thin-film thicknesses (25, 30, and 40 nm) on the electrical performance of solution-processed indium-zinc-oxide (IZO) thin-film transistors (TFTs). The structural properties of the IZO thin films were investigated by atomic force microscopy (AFM). AFM images revealed that the IZO thin films with thicknesses of 25 and 40 nm exhibit an uneven distribution of grains, which deforms the thin film and degrades the performance of the IZO TFT. Further, the IZO thin film with a thickness of 30 nm exhibits a homogeneous and smooth surface with a low RMS roughness of 1.88 nm. The IZO TFTs with the 30-nm-thick IZO film exhibit excellent results, with a field-effect mobility of $3.0({\pm}0.2)cm^2/Vs$, high Ion/Ioff ratio of $1.1{\times}10^7$, threshold voltage of $0.4({\pm}0.1)V$, and subthreshold swing of $0.7({\pm}0.01)V/dec$. The optimization of oxide semiconductor thickness through analysis of the surface morphologies can thus contribute to the development of oxide TFT manufacturing technology.

• 한국표면공학회지
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• 제50권5호
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• pp.352-359
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• 2017

The growth of nanocrystalline diamond films on a p-type poly silicon substrate was studied using microwave plasma chemical vapor deposition method. A 6 mm thick poly silicon plate was mirror polished and scratched in an ultrasonic bath containing slurries made of 30 cc ethanol and 1 gram of diamond powders having different sizes between 5 and 200 nm. Upon diamond deposition, the specimen scratched in a slurry with the smallest size of diamond powder exhibited the highest diamond particle density and, in turn, fastest diamond film growth rate. Diamond deposition was carried out applying different DC bias voltages (0, -50, -100, -150, -200 V) to the substrate. In the early stage of diamond deposition up to 2 h, the effect of voltage bias was not prominent probably because the diamond nucleation was retarded by ion bombardment onto the substrate. After 4 h of deposition, the film growth rate increased with the modest bias of -100 V and -150 V. With a bigger bias condition(-200 V), the growth rate decreased possibly due to the excessive ion bombardment on the substrate. The film grown under -150V bias exhibited the lowest contact angle and the highest surface roughness, which implied the most hydrophilic surface among the prepared samples. The film growth rate increased with the apparent activation energy of 21.04 kJ/mol as the deposition temperature increased in the range of $300{\sim}600^{\circ}C$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• 한국전기전자재료학회논문지
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• 제22권2호
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• 공업화학
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• 제34권4호
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• pp.383-387
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• 2023

범용적으로 고진공 성막 장비에서 사용되는 quartz crystal microbalance (QCM)는 두꺼운 필름이 quartz 위에 성막되는 경우, 크리스탈 고유의 진동에 영향을 주어 사용이 어려워진다. 본 논문에서는 실시간 필름 증착 공정 중에 센서의 손상이 없는 광학적 계측 방식을 통해 필름의 성막 속도를 측정하는 방법을 연구하였다. 기체 이동 경로로 지나가는 페럴린 가스 중 다이머에 의한 레이저의 산란 정도를 측정하여, 페럴린 공정의 분해부 온도가 감소할수록 페럴린 가스 중 다이머의 비율이 증가하는 것을 성공적으로 확인하였다. 또한, 성막된 필름의 특성을 확인한 결과, 분해부 온도가 감소할수록 필름의 두께와 haze가 증가한 것을 확인할 수 있었다. 우리는 연구 결과를 통해 개발한 안정적인 실시간 성막 속도 계측 시스템을 이용함으로써, 진공 공정을 통해 성막하는 페럴린 필름의 정밀한 성막 속도 제어에 활용하고자 한다.