• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.189-192
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• 2000

In this paper, we propose the novel test method to detect short and open faults in CMOS Op-amp. The proposed method is composed of two test steps - the offset and the high frequency test. Using HSPICE simulation, we get a 100％ fault coverage. To verify the proposed method, we design and fabricate the CMOS op-amp that contains various short and open faults through Hyundai 0.65$\mu\textrm{m}$ 2-poly 2-metal CMOS process. Experimental results of fabricated chip demonstrate that the proposed test method can detect short and open faults in CMOS Op-amp.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.81-90
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• 2004

This paper presents new testability measure based on learning, which can be useful in the deterministic process of test pattern generation algorithms. This testability measure uses the structural information that are obtained by teaming. The proposed testability measure searches for test pattern that can early detect the conflict in case of the hardest decision problems. On the other hand in case of the easiest decision problem, it searches for test pattern that likely results in the least conflict. The proposed testability measure reduces CPU time to generate test pattern that accomplishes the same fault coverage as that of the distance-based measure.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.10-22
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• 1998

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• Archives of Plastic Surgery
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• v.38 no.5
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• pp.663-668
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• 2011

Purpose: A modified free thenar flap was designed for coverage of volar finger defect with constant innervation using the palmar cutaneous branch of the median nerve. After clinical application of this flap, sensory results were evaluated in 6 cases. Methods: Patients were selected who have volar soft tissue defect with or without fingertip defect. The six cases of the innervated free thenar flap were performed since September 2009, and sensory outcomes were evaluated by the Semmes-Weinstein monofilament and two-point discriminator at four and half month after the surgery. Results: The Semmes-Weinstein Monofilament test revealed 3 cases showed 2.83, 1 case showed 3.61, 1 case showed 4.31 and 1 case showed 4.56. The static two-point discrimination test revealed 1 case showed 4 mm, 1 case showed 6 mm, 2 cases showed 9 mm, and 2 cases showed over 15 mm. The moving two-point discrimination test revealed 1 case showed 3 mm, 1 case showed 4 mm, 1 case showed 5 mm, 1 case showed 7 mm, and 2 cases showed over 15 mm. The donor sites showed no significant limitation of the thumb and neuroma formation. Conclusion: The innervated free thenar flap showed good sensory outcomes as a sensate free flap in a short time after surgery. It can be an option for coverage of volar finger defects that requires sensation.

• Journal of Fashion Business
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• v.9 no.5
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• pp.15-36
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• 2005

The purpose of this study was to provide for the useful fundamental data by developing an appearl sizing system according to body types for Chinese adult female. Thus, it was to improve of fittness and coverage rate of exporting domestic clothing to China. As a sample, 1360 female women was seleted aged between 19 and 50 who resident in Beijing and Shanghai in China for characterization body types and development of apparel sizing system by classifying them. As for the method of this study was made of 111 items by indirect measures done during Jun. 23 $\sim$ Aug. 7, 2004. Data analysis were processed by SPSS WIN 10.0 Program was used to for technical statistical analysis, ANOVA(t-test and F-test), factor analysis, duncan's multiple test. The results from the study were as follows: As they are getting older, the horizontal size and length categories related to width, thickness, and circumference increased, and the height and vertical size that show the vertical size of body reduced. 1. The women in the Shanghai area had large head width, head thickness and head circumference, the categories related to the height and head, and the women in the Beijing area had larger in terms of width, circumference, length, angle and other categories. 2. Chinese Adult women's constitutional components determined by factor analysis, six components could be identified: factor 1 : constitutional obesty and width size, factor 2 : longistudinal body size, factor 3 : shoulder form and size, factor 4 : longistudinal upper body size, factor 5 : longistudinal under body size, factor 6 : shoulder dropping.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.4
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• pp.587-604
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• 2021

Because the library cannot be run independently and used by many applications, it is important to detect vulnerabilities in the library. Fuzzing, which is a dynamic analysis, is used to discover vulnerabilities for the library. Although this fuzzing technique shows excellent results in terms of code coverage and unique crash counts, it is difficult to apply its effects to library fuzzing. In particular, a fuzzing executable and a seed corpus are needed that execute the library code by calling a specific function sequence and passing the input of the fuzzer to reproduce the various states of the library. Generating the fuzzing environment such as fuzzing executable and a seed corpus is challenging because it requires both understanding about the library and fuzzing knowledge. We propose a novel method to improve the ease of library fuzzing and enhance code coverage and crash detection performance by using a test framework. The systems's performance in this paper was applied to nine open-source libraries and was verified through comparison with previous studies.

• Journal of the Korean Society of Environmental Restoration Technology
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• v.23 no.6
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• pp.43-55
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• 2020

The study was performed in order to derive the management methods of revegetation space on embankment upper in the shoulder of expressway. The pilot study was conducted in 2013 on the test road section of the Jungbu Inland Expressway (Smart Highway) and continues to be monitored until 2020. In the test, three commonly used methods for weed control were applied. In the early two to three years, most of the methods were effective in controlling weeds. However, at the end of six years, weed suppression effects were different for each treatment. Vegetation coverage was 90% in the untreated control, 70-80% wood chip mulching method, 50-60% solidification method, and 20% sheet mulching method. The sheet method was found to be the most effective given the low vegetation coverage was effective in controlling weeds. The wood chip mulching method is promoting weed growth over time, and weeds are invading as the effect of soil hardening is reduced in the place where the soil hardener is treated. Among the methods applied in the test, mulching the sheet is the most effective, but it is important to use a durable sheet. In the future, it is necessary to find ways to control weeds on road shoulders, considering both economic and environmental aspects. For the proper management in the shoulder of expressway set target zone is needed. Clear standards for weed control on expressway should be established. And the technology to be applied must be durable for 3 years or more and must be able to suppress the amount of weeds to a level of 20% or less.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.86-96
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• 2000

The representative area among the ones whose cost increases as the integration ratio increases is the test area. As the relative cost of hardware decreases, the BIST method has been focued on as the future-oriented test method. The biggest drawback of it is the increasing test time to obtain the acceptable fault coverage. This paper proposed a BIST implementation method to reduce the test times. This method uses an input grouping and test point insertion method, in which the definition of test point is different from the previous one. That is, the test points are defined on the basis of the internal nodes which are the reference points of the input grouping and are merging points of the grouped signals. The main algorithms in the proposed method were implemented with C-language, and various circuits were used to apply the proposed method for experiment. The results showed that the test time could be reduced to at most $1/2^{40}$ of the pseudo-random pattern case and the fault coverage were also increased compared with the conventional BIST method. The relative hardware overhead of the proposed method to the circuit under test decreases as th e size of the circuit to be tested increases, and the delay overhead by the BIST utility is negligible compared to that of the original circuit. That means, the proposed method can be applied efficiently to large VLSI circuits.