• Title/Summary/Keyword: Termary logic circuit

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Implementation of Ternary Valued Adder and Multiplier Using Current Mode CMOS (전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현)

  • Seong, Hyeon-Kyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.9
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    • pp.1837-1844
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    • 2009
  • In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.