• Title/Summary/Keyword: Temporal logic

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Modeling Causality in Biological Pathways for Logical Identification of Drug Targets

  • Park, Il;Park, Jong-C.
    • Proceedings of the Korean Society for Bioinformatics Conference
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    • 2005.09a
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    • pp.373-378
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    • 2005
  • The diagrammatic language for pathways is widely used for representing systems knowledge as a network of causal relations. Biologists infer and hypothesize with pathways to design experiments and verify models, and to identify potential drug targets. Although there have been many approaches to formalize pathways to simulate a system, reasoning with incomplete and high level knowledge has not been possible. We present a qualitative formalization of a pathway language with incomplete causal descriptions and its translation into propositional temporal logic to automate the reasoning process. Such automation accelerates the identification of drug targets in pathways.

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Development of remote drum grappling device for Automation (물류자동화를 위한 드럼원격 취급장치 개발에 관한 연구)

  • 오승철;윤지섭
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1997.04a
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    • pp.739-742
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    • 1997
  • A remote drum grappling device coupled to the anti-swing crane has been developed by KAERI to cope with problems involved in manually treating low level waste drums. In order for this grappling device to be operated effectively, multi-sensors including CCD camera were employed. As an activity representation scheme of the device, Extended State Machine (ESM) was used to descibe its operation sequences. The performance testing of the device was conducted successfully, and consequently its application could be extendable to industrial operation environment.

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Expressing Service Specifications for Context-Awareness using temporal logic (상황 인식 시스템의 서비스 명세를 시제 논리로 표현하기)

  • Kim, Tae-Kyun;Cho, Min-Taek;Kwon, Gi-Hwon
    • Proceedings of the Korean Information Science Society Conference
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    • 2012.06b
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    • pp.253-254
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    • 2012
  • 상황 인식 시스템에서, 핵심 요소 중의 하나가 서비스 명세이다. 지금까지 서비스 명세를 표현하기 위해서 생성 규칙, 마크업 기반 언어 및 온톨로지 기반 언어 등이 사용되었다. 이들과는 다르게, 본 논문에서는 병행 시스템 및 반응형 시스템의 속성 명세에 널리 사용되는 시제 논리를 이용하여 상황 인식 서비스를 명세하고자 한다.

Formal Specification of ECG Signal (심전도 신호의 정형 명세)

  • Kwon, Hyeokju;Kwon, Hyuck;Kwon, Gihwon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2015.10a
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    • pp.1085-1087
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    • 2015
  • 본 논문에서는 심장의 전기활성도를 반영하는 ECG 신호 중 일부를 명세한다. 꾸준히 축적되었고 통용되는 ECG 신호의 비정형 명세를 정형 명세로 바꾸는 과정에서 선형 시제 논리보다 시간을 다루는 명세 및 양적 평가에 유리한 신호 시제 논리(Signal Temporal Logic)를 사용한다. ECG 신호를 감지했다는 가정하에 특징점을 추상화하여 신호를 맹세했고, 양적으로 평가해주는 모델 기발 실시간 ECG 모니터링 시스템의 신속한 개발 필요성을 제시한다.

Development of Music Therapy Using Signal Temporal Logic (신호 시제 논리를 활용한 음악치료 시스템 개발)

  • Park, Su-Jung;Ryu, In-Gon;Kwon, Gihwon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2015.10a
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    • pp.1080-1081
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    • 2015
  • 기존에 음악치료 시스템이 많이 활용되고 있다. 그러나 시스템 내의 문제가 고정적으로 되어있어서 수정 및 변경을 하기에 많은 불편함이 있다. 따라서 문제 생성의 유연성을 높이고자 신호 시제 논리를 활용한 음악치료 시스템을 개발해 본다.

Equivalence Checking of Finite State Machines with SMV (SMV를 이용한 유한 상태 기계의 동치 검사)

  • 권기현;엄태호
    • Journal of KIISE:Software and Applications
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    • v.30 no.7_8
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    • pp.642-648
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    • 2003
  • In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.

Specification and Proof of an Election Algorithm in Mobile Ad-hoc Network Systems (모바일 Ad-hoc 네트워크 시스템하에서 선출 알고리즘의 명세 및 증명)

  • Kim, Young-Lan;Kim, Yoon;Park, Sung-Hoon;Han, Hyun-Goo
    • Journal of Korea Multimedia Society
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    • v.13 no.7
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    • pp.950-959
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    • 2010
  • The Election paradigm can be used as a building block in many practical problems such as group communication, atomic commit and replicated data management where a protocol coordinator might be useful. The problem has been widely studied in the research community since one reason for this wide interest is that many distributed protocols need an election protocol. However, mobile ad hoc systems are more prone to failures than conventional distributed systems. Solving election in such an environment requires from a set of mobile nodes to choose a unique node as a leader based on its priority despite failures or disconnections of mobile nodes. In this paper, we describe a solution to the election problem from mobile ad hoc computing systems and it was proved by temporal logic. This solution is based on the Group Membership Detection algorithm.

The Method for Real-Time Systems Modeling Based On the Object and Temporal Logic (객체 및 시제논리에 기반한 실시간 시스템 모형화 방법)

  • Kim, Jung-Sool;Kang, Byung-Wook
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.6
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    • pp.1522-1536
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    • 1998
  • In this paper, we present a modeling method for the real-time systems. This method is based on the DARTS (Design Approach for Real-Time Systems) and widely extended to analysis phase. The DARTS method provides a good guideline for the real -time software design, but it uses structured analysis and does not provide a specification language. So. this paper provides extended DARTS modeling techniques to the analysis area based on the objects. Internal behavior of system showed by means of a NPN (Numerical Petri Net) for analysis, and the specification language is provided based on the temporal logic for transition synchronization sequence control. By the example, we identified the proposed method was applied well. And through the reachability graph, we verified whether the deadlocks may occur or not in the analysis phase before the design phase. Thus. it gives easy way to analysis, so that it will lead to the design phase naturally.

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A Study on Reasoning for Medical Expert Systems (의료용 전문가 시스템에서 추론에 관한 연구)

  • Kim, Jin-Sang;Shin, Yang-Kyu
    • Journal of the Korean Data and Information Science Society
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    • v.10 no.2
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    • pp.359-367
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    • 1999
  • We investigate a logical approach to represent medical knowledge, reason deductively and diagnostically. It is suggested that medical knowledge-bases can be formulated as a set of sentences stated in classical logic where each sentence reflects a doctor's knowledge about the human anatomy or his/her view of patient's symptoms. It is also suggested that a form of temporal reasoning can be captured within the same framework because each sentence can have a different truth value based on time. We apply our logical framework to formalize diagnostic reasoning, where the primary cause of illness is chosen among the set of minimal causation on the basis of abductive hypotheses. Most of our examples are given in the context of medical expert systems.

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Monitoring and Checking Concurrent Java Programs with HDTL (HDTL을 이용한 병렬 자바 프로그램의 모니터 링과 검사)

  • Cho, Seung-Mo;Kim, Hyung-Ho;Cha, Sung-Deok;Bae, Doo-Hwan
    • Journal of KIISE:Software and Applications
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    • v.29 no.5
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    • pp.345-354
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    • 2002
  • There have been many researches about monitoring and checking the implementations during run-time using formal requirement specification. They usually adopt temporal logics or their extensions to specify the requirements for the implementations. However, most of the systems fail to support the specification of requirements fir dynamic systems - systems whore components are created and removed during run-time. Unlike analysis or design models, most actual implementations are dynamic, so the notion of instances should be employed in the property specification language. In this paper, we show how we can monitor and check Java programs using our temporal logic for dynamic systems (HDTL). We suggest a framework in which the execution of Java programs are monitored and chocked against given HDTL requirements.