• Title/Summary/Keyword: Telematics device

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Low-voltage low-power comparator design techniques (저전압 저전력 비교기 설계기법)

  • 이호영;곽명보;이승훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.5
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    • pp.212-221
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    • 1996
  • A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.

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The Variation of Silicon Characteristic with Radiation Damage Effects (Radiation 손상에 기인한 실리콘 특성변화)

  • 장기현
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.15 no.4
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    • pp.26-32
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    • 1978
  • For a long life photovoltaic cell the degradation of the device characteristics with 1 MeV electron radiation must be known so as to be able to predict the life of the cell. Hence, a study was made of radiation damage effects on the bulk properties of the silicon crystal. From the results of the data, it is concluded that there appeared to be a steads rotate damage level reached in f type material.

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Microprocessor-Based Digital Controller Design with changing the Damping Ratio (감쇄비 변화를 마이크로프로세서로 이용한 계수형 제어기의 설계)

  • 정태원;김명환
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.19 no.1
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    • pp.35-40
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    • 1982
  • As a general-purpose device, the microprocessor has made a large impact on many area of engineering, In this paper, a controller has been implemented using microprocessors allowing the damping ratio ζ to be changed dynamically in control systems. The results show definite improvement in response time.

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Breakdown Voltage Improvement in SOI MOSFET Using Gate-Recessed Structure (게이트가 파인 구조를 이용한 SOI MOSFET에서의 항복전압 개선)

  • 최진혁;박영준;민홍식
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.159-165
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    • 1995
  • A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

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Study on the Improvement of Sub-Micron Channel P-MOSFET ($1{\mu}m$ 이하의 채널 길이를 가지는 P-MOSFET의 특성 개선에 관한 연구)

  • Park, Young-June
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.24 no.3
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    • pp.472-477
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    • 1987
  • In order to prevent the short-channel effects due to threshold voltage adjustment implantation in conventional n+ doped silicon gate process, a new approach involving automatic doping of polycide by boron during source and drain implantation is introduced. P-MOSFET devece fabricated by theis approach shows improved short channel characteristics than conventional device with n+ doped gate. Some concerns of adopting this approach in CMOS technology are addressed togetheer with some suggestions.

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Real Time Implementation of a Korean Speech Synthesizer (한국어 음성합성기의 실시간 구현에 관한 연구)

  • 임광일;이규태;조철우;이우선;신인철;이태원
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.2
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    • pp.176-181
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    • 1988
  • In this paper, the LPC speech synthesizer with Multipulsse excitation is implemented using general-purpose DSP \ulcornerD7720. As the driving function for synthesis filter is used in the amplitude and position of pulse, the Voice/Unvoice decision and pitch period detectioncan be excluded. The synthesizer is implemented with DSP device which is operated on the interrupt mehtod with main computer and on the DMA mehtod with D/A converter. The comparision of synthetic and original waveform, alogn with the listening test, proves the validity of this system.

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Molecular dynamics simulation of ultra-low energy ion implantation for GSI device technology development (GSI소자 개발을 위한 극 저 에너지 이온 주입에 대한 분자 역학 시뮬레이션)

  • 강정원;손명식;황호정
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.3
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    • pp.18-27
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    • 1998
  • Molecular dynamicsinvestigations of ion implantation considering point defect generation were performed with ion energies in the range of ~1keV, Simulation starts perfect diamond cubic lattice site. Stillinger-Weber potential and ZBL potential were used to calculate forces between atoms. We have simulated slowing-down of ion velocity, ion trajectory and coupled-coing between ion and silicon. We also discussed distribution of point defect using rdial distribution function. We found that interstitial produced by ion bombardment mainly formed interstitial cluster.

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An Ebers-Moll Model for Heterojunction Bipolar Transistor's (이종접합 쌍극성 트랜지스터의 Ebers-Moll 모델)

  • 박광민;곽계달
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.3
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    • pp.88-94
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    • 1993
  • In this paper, a simple Ebers-Moll Model for the heterojunction bipolar transistor is presented. Using the model structure for the npn type HBT, the current-voltage characteristics was analyzed. And from the obtained terminal currents, the Ebers-Moll equations were derived. Then substituting the physical parameters for heterojunction to those for homojunction, this model would be used to analyze the characteristics of single and/or duble heterojunction HBT's. And directly relating model parameters to device parameters, it would be also used to optimize the characteristics of HBT's. The simulated results using this model were in good agreement with experimental data.

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A new p-i-n/HBT photoreceiver design procedure for the optimum sensitivity (최적의 감도를 얻을 수 있는 p-i-n/HBT OEIC 광수신단의 새로운 설계방법)

  • ;;;M.B.Das
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.11
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    • pp.79-85
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    • 1995
  • In this paper, an epi layer and a device structure for InP/InGaAs p-i-n/HBT OEIC is designed for a receiving frontend of high speed optical communications. A 3 stage transimpedance circuit using the p-i-n/HBT device is also designed by SPICE simulations for a high sensitivity including ISI noises at a given bit rate. Our simulations show that the Personick's assumption which is not commonly satisfied have estimated a photoreceiver sensitivity too high, so thus we have to also consider ISI noises in OCIC receiver designs.

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Buck converter with new driving circuit in TV poer system (TV 전원장치에서 새로운 구동 회로에 의한 buck converter)

  • 정진국
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.3
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    • pp.56-61
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    • 1996
  • In this paper, new buck converter of a TV power system is presented. First, we devised a revised driving circuit for an emitter-coupled type buck converter, by which it is possible to reduce the material cost of transformers and voltage stress of power device. Secondly, we adopted a hybrid oscillation technique. When TV system is in off-stage, initial standby power which is necessary for remote controllable TV system is supplied by self-oscillating mode. Main power which is necessry in TV system bing on state is provided by an externally triggered oscillating mode. The switching frequency is synchronized to the oscillating frequency of horizontal deflection in TV, by which we can reduce picture noises and the size of power transformer. Thirdly, a simple error amplifier is inserted to the feed-back loop to keep the output voltage constant which means pulse width modulatio mode is added in driving part of power device. Finally, we showed by experiments that our proposed converter performs well enough to be close to the theoretically predicted values.

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