• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.63-69
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• 1998

In this paper, we propose a new Bit-Rate control algorithm based on bit usage matching to substitute encoded GOP(s) for new GOP(s) in MPEG-2 bitstream. It iteratively encodes current picture according to quantization value of previous picture and records bit-usage of each slice until nearly target bits are used. With target bits falling in two output bits, quantization value of slice should be changed to alleviate output bit error. We use recorded bit-usage information to decide which slices should be encoded with one quantization value and others with another. As every macroblock has different activity, we change macroblock quantization value using slice quantization value and activity value. The simulation results demonstrate that the fluctuation of the output bits can be kept within few-several tens of bits while maintaining the quality of the reconstructed pictures at a relatively stable level.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.75-80
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• 2009

RSA cryptoprocessors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, a fast 32bit modular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.740-743
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, $32b^*32b$ multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the stalks flag. In this paper, a fast 32bit nodular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1424-1435
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• 2000

A bit-rate controller that can achieve a constant bit rate when coding object-based video sequences is an important part to achieve an adaptation to bit-rate constraints, desired video quality, distribution of bits among objects, relationship between texture and shape coding, and determination of frame skip or not. Therefore we design content-based bit rate controller which will be used for relevant bit-rate control. The implementation is an extension of MPEG-4 rate control algorithm which employs a quadratic rate-quantizer model. The importance of different objects in a video is analyzed and segmented into a number of VOPs which are adaptively bit-allocated using the object-based modelling. Some test sequences are observed by a number of non-experts and interests in each object are analysed. The initial total target bit-rate for all objects is obtained by using the proposed technique. Then the total target bits are jointly analyzed for preventing from overflow or underflow of the buffer fullness. The target bits are distributed to each object in view of its importance, not only of statistical analysis such as motion vector magnitude, size of object shape, and coding distortion of previous frame. The scheme is compared with the rate controller adopted by the MPEG-4 VM8 video coder by representing their statistics and performance.

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.3
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• pp.446-458
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• 2013

Recently, energy-efficient cellular transmission has received considerable research attention to improve the energy efficiency of wireless communication. In this paper, we consider a cellular network consisting of one base station (BS) and multiple user terminals and explore the network coding for enhancing the energy efficiency of cellular downlink transmission from BS to users. We propose the network coded cellular transmission scheme and conduct its energy consumption analysis with target outage probability and data rate requirements in Rayleigh fading environments. Then, the energy efficiency in Bits-per-Joule is further defined and analyzed to evaluate the number of bits delivered per Joule of energy cost. Numerical results show that the network coded cellular transmission significantly outperforms the traditional cellular transmission in terms of energy efficiency, implying that given a Joule of energy cost, the network coded cellular transmission scheme can deliver more bits than the traditional cellular transmission.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.06a
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• pp.31-36
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• 1997

Bit allocation is a critical problem in video encoding such as MPEG. To improve the quality of the reconstructed sequence for a given bit rate, the assigned target bits for a group of pictures (GOP) must be allocated to each picture efficiently. In this paper, we derive a target bit allocation algorithm for more efficient rate control, by assuming that the average rate-distortion curve for an input source is logarithmic. This target bit allocation is based on Shannon's rate-distortion theory, which deals with the minimization of source distortion subject to a channel rate constraint. Simulation results show that the proposed target bit allocation algorithm provides better performance than the one in MPEG-2 Test Model 5 (TM5).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1193-1200
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• 2010

This paper presents a new adaptive macroblock quantization algorithm which generates the output bits corresponding to the target bit budget. The H.264 standard uses various coding modes and optimization methods to improve the compression performance, which makes it difficult to control the amount of the generated traffic accurately. In the proposed scheme, linear regression analysis is used to analyze the relationship between the bit rate of each macroblock and the quantization parameter and to predict the MAD values. Using the predicted values, the quantization parameter of each macroblock is determined by the Lagrange multiplier method and then modified according to the difference between the bit budget and the generated bits. It is shown by experimental results that the new algorithm can generate output bits accurately corresponding to the target bit rates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.65-70
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b${\times}$32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.