• Journal of Yeungnam Medical Science
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• v.4 no.1
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• pp.123-128
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• 1987

To estimate the prevalence of hypertension among the aged in urban area, the blood pressure was examined on the subjects of 565 men and 762 women of 65 years old and older among the residents of Nam-Ku and Soosung-Ku in Taegu between January and December, 1986. The mean systolic blood pressure was $136.0{\pm}25.01mmHg$ in male and $133.0{\pm}24.56mmHg$ in female. The mean diastolic blood pressure was $83.7{\pm}14.41mmHg$ in male and $82.4{\pm}14.43mmHg$ in female. There was no significant differences between male and female in both mean systolic and diastolic blood pressure. According to WHO category, the prevalence of pure systolic hypertension (${\geq}$160/<95mmHg) was 7.8% in male and 6.8% in female. The prevalence of pure diastolic hypertension(<160/${\geq}$95mmHg) was 6.0% in male and 3.9% in female. The prevalence of both systolic and diastolic hypertension (${\geq}160/{\geq}95mmHg$) was 13.5% in male and 12.9% in female. According to joint National Committee category, the percentage of normal blood pressure (/<90mmHg) was 46.7% in male and 50.8% in female. The prevalence of mild hypertension (/90=104mmHg) was 34.5% in male and 34.6% in female. The prevalance of moderate hypertension (/105=144mmHg) was 5.1% in male and 2.5% in female. The prevalence of severe hypertension (/${\geq}$115mmHg) was 2.3% in male and 3.0% in female. The prevalence of borderline isolated systolic hypertension (140-159/<90mmHg) was 9.0% in male and 6.6% in female. The prevalence of isolated systolic hypertension (${\geq}$160/<90mmHg) was 2.3% in male and 2.5% in female.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.103-110
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• 1996

In this paper, we propose a unified systolic array for the computation of the 2D discrete cosine transform/discrete sine transform/discrete hartley transform (DCT/DST/DHT). The unified systeolic array for the 2D DCT/DST/DHT is a generalization of the unified systolic array for the 1D DCT/DST/DHT. In order to calculate the 2D transform, we compute 1D transforms along the row, transpose them, and obtain 1D transforms along the column. When we compare the proposed systolic array with the conventional method, our architecture exhibits a lot of advantages in terms of latency, throughput, and the number of PE's. The simulation results using very high speed integrated circuit hardware description language (VHDL), international standard language for hardware description, show the functional validity of the proposed architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.7
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• pp.739-748
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• 1992

A CGM iterative systolic algorithm to solve large sparse linear systems of equations is presented. For implementation of the algorithm, a systolic array using the stripe structure is proposed. The matrix A is decomposed into a strictly lower triangular matrix, a diagonal matrix, and a strictly up-per triangular matrix, and the two formers and the tatter· are concurrently computed by different linear arrays. Hence, the execution time of this approach Is reduced to half of the execution time of the that a linear array is used. computation of the Irregularly distributed sparse matrix can be executed effectively by using the stripe structure.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.851-858
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• 1988

In this paper, we propose two different VLSI architectures for the parallel computation of DCT (discrete cosine transform) algorithm. First, it is shown that the DCT algorithm can be implemented on the existing systolic architecture for the DFT(discrete fourier transform) by introducing some modification. Secondly, a new prime factor DCT algorithm based on the prime factor DFT algorithm is proposed. And it is shown that the proposed algorihtm can be implemented in parallel on the systolic architecture for the prime factor DFT. However, proposed algorithm is only applicable to the data length which can be decomposed into relatively prime and odd numbers. It is also found that the proposed systolic architecture requires less multipliers than the structures implementing FDCT(fast DCT) algorithms directly.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.8
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• pp.1178-1186
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• 1989

In this paper, a systolic array for polyadic-nonserial DP problems is designed, the performance is analyzed and the efficient operating method is proposed. The algorithm is transformed to remove the broadcasting and global communication paths in the data dependence step by step. The transformed algorithm is mapping to the systolic array using the method proposed by D. I. Moldovan. The designed array is homogenous, had the processing elements of (n+1)/2 and 2n computation time ( n is the size of problem). In case of being many problems to process, the efficiency of array can be upward by inputing the problems successively. The interval between the initiations of two successive proboem instances is [n/2]+1 and the speed-up is about 4. The processor utilizations of each case are calculated.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.11-20
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• 1994

We propose two architectures using two dimensional systolic arrays for the DCT/DST/DHT. One decomposes the N-point DCT/DST/DHT into even-and odd-numbered frequency samples, and then computes them independently at the same time. In addition, the proposed architecture can be used for the IDCT/IDST/IDHT. Anogher is the modified version for the DHT/IDHT. Two proposed architectures generate outputs sequentially using real multiplications and additions. As compared to the conventional methods the proposed systolic arrays exhibit many advantages in terms of simplicity of the processing element (PE), latency, and throughput. Teh simulation results using VHDL, international standard language for hardware description, show the effectiveness of the proposed architecture.

• Journal of the Ergonomics Society of Korea
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• v.11 no.1
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• pp.67-79
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• 1992

Cardiac systolic time intervals (STLs) and Heather index (HI) were used to access changes in left ventricular function of six male subjects exposed to postural changes,$0^{\circ}C$, ${\pm}2^{\circ}C$, ${\pm}45^{\circ}C$, ${\pm}90^{\circ}C$, Significant prolongation of the pre-ejection period (PEP) and PEP/ LVET ratio, shortening of the left ventricular ejection time (LVET), STI, HI and $1/PEP^{2}$were observed during exposure to both $+45^{\circ}C $ and $+90^{\circ}C $But the values measured during $-45^{\circ}C $ and$-90^{\circ}C $ were reversed. Changes in fluid shift, filling volume, preload, after load and sympathetic activities may account for the observed findings. Early response of cardiac foctions was recorded using impedance cardiography. This method is very simple but accurate. Thus it will be useful in this aerospace and work physiology. In conclusion, STIs appear to provide reliable noninvasive method for examining changes of cardiac function during exposure to postural changes.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2222-2232
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• 1999

This paper proposed a Systolic Arrays architecture for computing edge detection on images. It is very difficult to be processed images to real time because of operations of local operators. Local operators for computing edge detection are to be used in many image processing tasks, involve replacing each pixel in an image with a value computed within a local neighborhood of that pixel. Computing such operators at the video rate requires a computing power which is not provided by conventional computer. Through computationally expensive, it is highly regular. Thus, this paper presents a systolic arrays for tasks such as edge detection and laplacian, which are defined in terms of local operators.

• Journal of Internet Computing and Services
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• v.7 no.1
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• pp.49-57
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.8-13
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• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.