• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.6
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• pp.2207-2213
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• 2010

A new scheme for variable structure control design which is based on eigenvalues assignment of sliding mode is developed. In conventional methods, generally, specific type of system matrix like canonical or regular form is required to construct a switching surface. Furthermore, the methods are not explicit. The new method in this paper solved the problems. No special type of system matrix is required and very explicit. It is shown that the switching surface can be constructed and determined uniquely without any dependency on the system form. The proposed method is based on the fact that the dynamics of sliding mode is determined by system zeros. Finally, a numerical example is given to verify the validity of the results studied in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.450-453
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• 2017

In this abstract, the FPGA system using solar tracking is introduced. Solar tracking system combined with sensor tracking and solar altitude programming is utilized. The sensor tracking system consists of image sensor, light sensor, and the programs for sun altitude received by the computer. The sun altitude is received from the national weather database by wireless communication. The goal is to have maximum energy generation efficiency using bi-directional tracking and mixed tracking with FPGAs that are relatively inexpensive in terms of developing and programming the system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.31-38
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• 2008

This paper describes sensor network system implementation for the IEEE 1451.2 standard which guarantees compatibilities between various wired sensors. The proposed system consists of the Network Capable Application Processor(NCAP) in the IEEE 1451.0, the Transducer Independent Interface(TII) in the IEEE 1451.2, the Transducer Electronic Data Sheet(TEDS) and sensors. The research goal of this study is to minimize and optimize system complexity for IC design. The NCAP is implemented using C language in personal computer environment. TII is used in the parallel port between PC and an FPGA application board. Transducer is implemented using Verilog on the FPGA application board. We verified the proposed system architecture based on the standards.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.237-243
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• 2007

In this paper, we propose the Real-time Dead-Pixel Detection and Compensation System for mobile camera and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However a conventional Dead-Pixel Detection Algorithm is disable to detect neighboring dead pixels and it degrades image quality by wrong detection and compensation. To detect dead pixels the proposed system is classifying dead pixels into Hot pixel and Cold pixel. Also, the proposed algorithm is processing line-detector and $5{\times}5$ window-detector consecutively. The line-detector and window-detector can search dead pixels by using one-dimensional(only horizontal) method in low frequency area and two-dimensional(vertical and diagonal) method in high frequency area, respectively. The experimental result shows that it can detect 99% of dead pixels. It was designed in Verilog hardware description language and total gate count is 23K using TSMC 0.25um ASIC library.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.18-20
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• 1998

본 논문에서는 RISC Microprocessor Core 설계에 대한 기반 기술을 확립하여, GPS(Global Positioning System) 같은 Embedded 시스템 등에서 주로 사용되어 지고 있는 ARM사의 ARM7 CPU와 이진 호환이 가능한 Microprocessor를 설계하고자 하였다. 이를 위하여 RISC Microprocessor의 기본적인 구조를 바탕으로 하여 ARM7 CPU와의 호환을 위하여 ARM7 CPU의 명령어들이 주어진 Clock안에 수행될 수 있도록 설계를 하였고, 여러 모듈을 원활히 공유할 수 있도록 내부에 공유 버스를 설계하였다. 설계를 위해서 Verilog-HDL(Hardware Description Language)을 사용하였으며, Microprocessor를 기술하는데 있어서 Behavioral 구조와 RTL(Register Transfer Level) 구조를 혼합하여 사용하였다. 설계된 Microprocessor의 동작은 면적과 타이밍의 최적화를 거친 후 Cwaves 툴을 사용하여 실질적인 ARM7의 명령어들을 수행하면서 검증하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.33-37
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• 2013

In this paper, we introduce a SDRAM controller implemented on FPGA. Modern embedded system adopts SDRAM as a memory to meet the high capacity memory demands. Our SDRAM controller is written in Verilog and verified on an FPGA, demonstrating the functionality along with ARM Cortex-M0, supporting AMBA AHB.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2645-2648
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• 2003

In this paper, real-time and reconfiguable hardware filter for face recognition is proposed and implemented on FPGA chip using verilog-HDL. In general, face recognition is considerably difficult because it is influenced by noises or the variation of illumination. Some of the commonly used filters such s histogram equalization filter, contrast stretching filter for image enhancement and illumination compensation filter are proposed for realizing more effective illumination compensation. The filter proposed in this paper was designed and verified by debugging and simulating on hardware. Experimental results show that the proposed filter system can generate selective set of real-time reconfiguable hardware filters suitable for face recognition in various situation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.