• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.34-44
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• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• Journal of Internet Computing and Services
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• v.9 no.6
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• pp.1-13
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• 2008

Trusted Computing is a hardware-based technology that aims to guarantee security for machines beyond their users' control by providing security on computing hardware and software. TPM(Trusted Platform Module), the trusted platform specified by the Trusted Computing Group, acts as the roots for the trusted data storage and the trusted reporting of platform configuration. Data sealing encrypts secret data with a key and the platform's configuration at the time of encryption. In contrast to the traditional data sealing based on binary hash values of the platform configuration, a new approach called property-based data sealing was recently suggested. In this paper, we propose and analyze a new property-based data sealing protocol using the weakest precondition concept by Dijkstra. The proposed protocol resolves the problem of system updates by allowing sealed data to be unsealed at any configuration providing the required property. It assumes practically implementable trusted third parties only and protects platform's privacy when communicating. We demonstrate the proposed protocol's operability with any TPM chip by implementing and running the protocol on a software TPM emulator by Strasser. The proposed scheme can be deployed in PDAs and smart phones over wireless mobile networks as well as desktop PCs.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.1
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• pp.219-227
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• 2017

Current military command information system uses electronic equipment a lot on which semiconductor chip is attached. It seems its' importance will increase more with latest information communication technology developing. Electronic equipment which uses electricity contains regular tolerance to high output electric signal. And EMC specification is the standardized of this electronic equipment's tolerance. On the other hand, the Institute of Atomic Energy Research has ever declared that high output electromagnetic pulse(EMP) will be broken out within the radius of 170Km when 10kt nuclear explosion occurs at an altitude of 40Km above Seoul. Then, the region suffer from the damage of most electronic equipments. Therefore, the norm to protect the influences in that case is defined by EMP protection specification. Most common electronic equipments meet the EMC norm, but there is no way to check whether they meet the EMP norm or not. That is because it is difficult to check whether they meet EMP protection norm and is on the matter of cost. Except inevitable cases, there is no review of checking whether they meet the norm or not. Considering the above, in this research, we speculate about the measures to improve military EMP protection ability by analyzing the EMC-EMP correlation and checking the EMP protection ability of general electronic equipment through the analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.128-135
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• 2013

This paper presents a high dimming ratio Power-LED driver IC with high power which is capable of controlling LEDs. In order to accomplish a high dimming ratio LED driver, the preloading inductor current methodology is proposed for the power stage of the proposed method to achieve the fast transient response time during the Power-LED load switching. The information containing the current flowing on the LEDs can be utilized to predict the amount of the current on the inductor. The minimum LED current rising time of existing high dimming ratio Power-LED driver is limited by $3{\mu}s$, however that of the proposed high dimming ratio Power-LED driver is reduced about 1/10. The LED driver is implemented with 0.35um 60V BCDMOS 2-poly 4-metal process. The measurement results show that the proposed LED driver system features the minimum rising time as small as 240ns at the dimming frequency of 1KHz with a 12V of input voltage, nine white LEDs and 353mA of LED current. The LED rising time and power conversion efficiency of the chip are measured to be 240ns and 93.72%, respectively.

• Journal of Digital Convergence
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• v.11 no.4
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• pp.221-227
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• 2013

RFID is an automatic identification technology that can control a range of information via IC chips and radio communication. Also known as electronic tags, smart tags or electronic labels, RFID technology enables embedding the overall process from production to sales in an ultra-small IC chip and tracking down such information using radio frequencies. Currently, RFID-based application and development is in progress in such fields as health care, national defense, logistics and security. RFID structure consists of a reader that reads tag information, a tag that provides information and the database that manages data. Yet, the wireless section between the reader and the tag is vulnerable to security issues. To sort out the vulnerability, studies on security protocols have been conducted actively. However, due to difficulties in implementation, most suggestions are concerned with theorem proving, which is prone to vulnerability found by other investigators later on, ending up in many troubles with applicability in practice. To experimentally test the security of the protocol proposed here, the formal verification tool, CasperFDR was used. To sum up, the proposed protocol was found to be secure against diverse attacks. That is, the proposed protocol meets the safety standard against new types of attacks and ensures security when applied to real tags in the future.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.3
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• pp.50-56
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• 2010

In this paper, compact broad-band antenna using circular spiral slot and CPW (coplanar waveguide) feed is proposed. The proposed antenna is designed on the same plane of the substrate by using CPW fed structure, archimediean spiral slot structure. So it was achieved both the size of compact antenna and the broad band. A archimediean spiral slot structure is introduced for resonance of medium band operation. The distances of a CPW feeder line and a ground plane are modified for impedance matching and lower/higher band operation. The proposed antenna has a compact size ($8mm\;{\times}\;13mm$) and it is etched on the FR-4 (relative dielectric constant 4.4, thickness 0.8mm) dielectric substrate. The simulated impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 5.98GHz (4.1GHz ~ 10.08GHz) and 3.97dBi, respectively. The measured impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 6.02GHz (4.48GHz ~ 10.5GHz) and 2.68dBi, respectively. The simulation and measured result shows good impedance matching and radiation pattern over the interesting frequency bands. It can be applied to antenna of broad-band wireless communication system.

• Journal of Digital Contents Society
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• v.10 no.2
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• pp.199-207
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• 2009

The Q-switching the shutter or the different optical science element puts in within the laser light resonator and the storehouse departs from the within the resonator it loses the mortar and the reversal distribution which when is sufficient creates from within the active medium, opens the shutter instantaneously and it is to do to be made to emit with the light where the energy which is accumulated within the resonator is strong very. Like this Q-switching of laser resonator--It decreases factor increasing suddenly to make. To method of Laser Q-switching mechanical switching methods, electro-optic switching methods and switching by saturable absorber methods, acousto-optic switching method etc. 4 kind are being used on a large scale. In these people the conversion which is electric in compliance with the effect which is electrooptics is widely being used the Q-switching pulse of short pulse width because being it will be able to create. Consequently, Pockel cell where it has the quality of electrooptics effect) the Q-it is become known that it is suitable it uses with switch. From the research which it sees FET and one-chip microprocessor where it is a switching element and pulse transfomer to plan and produce pockel cell Q-switch driving gears, pulse style Nd: It applied in YAG Laser system and it investigated and researched the operating characteristic of the Q-switch. Also, the Q-switch leads and Nd where it is output: YAG with forecast in compliance with a theoretical calculation it comes to buy laser beam side politics it compared and laser beam qualities which had become Q-switching it analyzed.