• Korean Journal of Optics and Photonics
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• v.12 no.5
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• pp.382-388
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• 2001

KITSAT-3, launched at May 26 1999, has an earth observation optical payload named MEIS (Multi-spectral Earth Imaging System). The MEIS is a Managin mirror telescope of aperture size of 95mm, and it images the ground with the ground sampling distance of 13.8m over 48km at the altitude of 720km using three different observations bands. This paper first presents the design and then the optics, relating results of manufacturing, integration and test. Finally it briefly discusses the current status of MEIS operation.

• Nuclear Engineering and Technology
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• v.55 no.3
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• pp.939-946
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• 2023

Comprehensive Research Facility for Fusion Technology (CRAFT) is an integration of different demonstrating or testing facilities, which aim to develop the critical technology or composition system towards the fusion reactor. Due to the importance and challenge of the negative ion based neutral beam injection (NNBI), a NNBI test facility is included in the framework of CRAFT. The initial object of CRAFT NNBI test facility is to obtain a H⁰ beam power of 2 MW at the energy of 200-400 keV for the pulse duration of 100 s. Inside the negative ion accelerator of NNBI system, the interactions of the negative ions with the background gas and electrodes can generate abundant stray electrons. The stray electrons can be further accelerated and dumped on the electrodes or eject from the accelerator. The stray electrons, including the ejecting electrons, cause the unwanted particle and heat flux onto the electrodes and the inner components of beamline (especially the temperature sensitive cryopump). The suppression of the stray electrons from the CRAFT accelerator is carried out via a series of design and simulation works. The paper focuses the influence of different magnetic field configurations on the stray electrons and the character of the ejecting electrons.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.08a
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• pp.142-147
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• 1998

Recently, 8 kb/s CS-ACELP coder of G.729 is atandardized by ITU-T SG15 and it has been reported that the speech quality of G729 is better than or equal to that of 32kb/s ADPCM. However G.729 is the fixed rate speech coder, and it does not consider the property of voice activity in mutual conversation. If we use the voice activity, we can reduce the average bit rate in half without any degradations of the speech quality. In this paper, we propose an efficient variable rate algorithm for G.729. The variable rate algorithm consists of two main subjects, the rate determination algorithm and algorithm, we combine the energy-thresholding method, the phonetic segmentation method by integration of various feature parameters obtained through the analysis procedure, and the variable hangover period method. Through the analysis of noise features, the 1 kb/s sub rate coder is designed for coding the background noise signal. So, we design the 4 kb/s sub rate coder for the unvoiced parts. The performance of the variable rate algorithm is evaluated by the comparison of speed quality and average bit rate with G.729. Subjective quality test is also done by MOS test. Conclusively, it is verified that the proposed variable rate CS-ACELP coder produced the same speech quality as G.729, at the average bit rate of 4.4 kb/s.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.131-138
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• 2007

Plain old Web Services came true a services integration with use the XML that will be able to define a platform-independent document format in basic document format. Hut, the XML document decreases the efficiency of the whole application program with connects frequently in relatively slow communication media like network environment, embedded system or use the resource limited small-sized instrument like mobile. In this paper, we implemented the algorism of Fast Infoset, which can convert XML into Fast XML using the Fast Inoset method and PER encoding rules in ASN.1 and constructs Test Bed. Also, it is compared with the existing pure XML message method in difference of process performance after encoding SOAP messages of XML basis when constructing web service.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.10
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• pp.805-812
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• 2013

The operational flight program(OFP) which has the functions of I/O processing with avionics, flight control logic calculation, fault diagnosis and redundancy mode is embedded in the flight control computer of Smart UAV. The OFP was developed in the environment of PowerPC 755 processor and VxWorks 5.5 real-time operating system. The OFP consists of memory access module, device I/O signal processing module and flight control logic module, and each module was designed to hierarchical structure. Memory access and signal processing modules were verified from bench test, and flight control logic module was verified from hardware-in-the-loop simulation(HILS) test, ground integration test, tethered test and flight test. This paper describes development environment, software structure, verification and management method of the OFP.

• Journal of Korean Society for Geospatial Information Science
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• v.16 no.2
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• pp.67-76
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• 2008

Recently, one of the most outstanding technological characteristics of aerial survey is an application of Direct Georeferencing, which is based on the integration of main sensing sensors such as aerial camera or Lidar with positioning sensors GPS and IMU. In addition, a variety of digital aerial mapping cameras is developed and supplied with the verification of their technical superiority and applicability. In accordance with this requirement, the development of a multi-looking aerial photographing system is just making 3-D information acquisition and texture mapping possible for the dead areas arising from building side and high terrain variation where the use of traditional phptogrammetry is not valid. However, the development of a multi-looking camera integrating different sensors and multi-camera array causes some problems to conduct time synchronization among sensors and their geometric and radiometric calibration. The establishment of a test field for aerial sensor calibration is absolutely necessary to solve this problem. Therefore, this paper describes investigations for photogrammetric Test Field of foreign countries and suggest an establishment scheme for domestic test field.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Journal of Biomedical Engineering Research
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• v.37 no.5
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• pp.168-177
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• 2016

In this paper we present an implantable pressure sensor to measure real-time blood pressure by monitoring mechanical movement of artery. Sensor is composed of inductors (L) and capacitors (C) which are formed by microfabrication and direct bonding on two biocompatible substrates (quartz). When electrical potential is applied to the sensor, the inductors and capacitors generates a LC resonance circuit and produce characteristic resonant frequencies. Real-time variation of the resonant frequency is monitored by an external measurement system using inductive coupling. Structural and electrical simulation was performed by Computer Aided Engineering (CAE) programs, ANSYS and HFSS, to optimize geometry of sensor. Ultrafast laser (femto-second) cutting and MEMS process were executed as sensor fabrication methods with consideration of brittleness of the substrate and small radial artery size. After whole fabrication processes, we got sensors of $3mm{\times}15mm{\times}0.5mm$. Resonant frequency of the sensor was around 90 MHz at atmosphere (760 mmHg), and the sensor has good linearity without any hysteresis. Longterm (5 years) stability of the sensor was verified by thermal acceleration testing with Arrhenius model. Moreover, in-vitro cytotoxicity test was done to show biocompatiblity of the sensor and validation of real-time blood pressure measurement was verified with animal test by implant of the sensor. By integration with development of external interrogation system, the proposed sensor system will be a promising method to measure real-time blood pressure.