• Convergence Security Journal
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• v.24 no.1
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• pp.35-42
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• 2024

Multi-tenancy architecture plays a crucial role in cloud-based services and applications, and data isolation within such environments has emerged as a significant security challenge. This paper investigates various data isolation methods including schema-based isolation, logical isolation, and physical isolation, and compares their respective advantages and disadvantages. It evaluates the practical application and effectiveness of these data isolation methods, proposing security considerations and selection criteria for data isolation in the development of multi-tenant websites. This paper offers important guidance for developers, architects, and system administrators aiming to enhance data security in multi-tenancy environments. It suggests a foundational framework for the design and implementation of efficient and secure multi-tenant websites. Additionally, it provides insights into how the choice of data isolation methods impacts system performance, scalability, maintenance ease, and overall security, exploring ways to improve the security and stability of multi-tenant systems.

• Korean Journal of Construction Engineering and Management
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• v.1 no.2 s.2
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• pp.98-107
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• 2000

Increased use of computers in AEC (Architecture, Engineering and Construction) has expanded the amount of information gained from CAD (Computer Aided Design), PMIS (Project Management Information System), Structural Analysis Program, and Scheduling Program as well as making it more complex. And the productivity of AEC industry is largely dependent on well management and efficient reuse of this information. Accordingly, such trend incited much research and development on ITC (Information Technology in Construction) and CIC (Computer Integrated Construction) to be conducted. In exemplifying such effort, many researchers studied and researched on IFC (Industry Foundation Classes) since its development by IAI (International Alliance for Interoperability) for the product based information sharing. However, in spite of some valuable outputs, these researches are yet in the preliminary stage and deal mainly with conceptual ideas and trial implementations. Research on unveiling the process of the IFC application development, the core of the Design Information management system, and its applicable plan still need be done. Thus, the purpose of this paper is to determine the technologies needed for Design Information management system using IFC, and to present the key roles and the process of the IFC application development and its applicable plan. This system play a role to integrate the architectural information and the structural information into the product model and to group many each product items with various levels and aspects. To make the process model, we defined two activities, 'Product Modeling', 'Application Development', at the initial level. Then we decomposed the Application Development activity into five activities, 'IFC Schema Compile', 'Class Compile', 'Make Project Database Schema', 'Development of Product Frameworker', 'Make Project Database'. These activities are carried out by C++ Compiler, CAD, ObjectStore, ST-Developer, and ST-ObjectStore. Finally, we proposed the applicable process with six stages, '3D Modeling', 'Creation of Product Information', 'Creation and Update of Database', 'Reformation of Model's Structure with Multiple Hierarchies', 'Integration of Drawings and Specifications', and 'Creation of Quantity Information'. The IFCs, including the other classes which are going to be updated and developed newly on the construction, civil/structure, and facility management, will be used by the experts through the internet distribution technologies including CORBA and DCOM.

• Journal of Internet Computing and Services
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• v.6 no.6
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• pp.85-97
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• 2005

In this paper, we construct the traffic information database by using the acquired data from the traffic information devices installed in road network, and, by referring to this database, propose the intersection simulation system which can dynamically manage the real-time traffic flow for each section of road from the intersections, This system consists of hierarchical 3 parts, The lower layer is the physical layer where the traffic information is acquired on an actual road. The traffic flow control framework exists in the middle layer. The framework supports the grouping of intersection, the collection of real-time traffic flow information, and the remote monitoring and control by using the traffic information of the lower layer, This layer is designed by extending the distributed object group framework we developed. In upper layer, the intersection simulator applications controlling the traffic flow by grouping the intersections exist. The components of the intersection application in our system are composed of the implementing objects based on the Time-triggered Message-triggered Object(TMO) scheme, The intersection simulation system considers the each intersection on road as an application group, and can apply the control models of dynamic traffic flow by the road's status. At this time, we use the real-time traffic information collected through inter-communication among intersections. For constructing this system, we defined the system architecture and the interaction of components on the traffic flow control framework which supports the TMO scheme and the TMO Support Middleware(TMOSM), and designed the application simulator and the user interface to the monitoring and the controlling of traffic flow.

• Journal of Korea Multimedia Society
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• v.2 no.3
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• pp.277-288
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• 1999

A distributed multimedia school system is developed for the multimedia classroom at high school and university. The system is designed and implemented for students to improve the learning efficiency through the personalized multimedia contents and pace of learning. The previously developed multimedia information retrieval systems have some limitations on being applied to the multimedia classroom: expensive cost per stream or poor retrieval quality inappropriate for education, unscalability of system and service, unfamiliar proprietary client environment, and difficulty for teachers to use the authoring tools and manage the authored teaching materials. The system we developed overcomes the above problems. It is so scalable as to be applicable not only to a segmented classroom but also to the world wide Internet. The stream server is one of the components of the system: stream servers clients, a service gateway system, and a authoring management system. This paper describes the design and implementation of the stream server. A single stream server can simultaneously playback the multimedia streams as many as clients at one classroom. This is achieved only by the software engine without any changes of the hardware architecture. The systematic coupling with other components gives the scalability of the system and the flexibility of services.

• Journal of Internet Computing and Services
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• v.10 no.4
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• pp.87-103
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• 2009

Grid computing is an expanded technology of distributed computing technology to use low-cost and high-performance computing power in various fields. Although the purpose of Grid computing focuses on large-scale resource sharing, innovative applications, and in some case, high-performance orientation, it has been used as conventional distributed computing environment like clustered computer until now because Grid middleware does not have common sharable information system. In order to use Grid computing environment efficiently which consists of various Grid middlewares, it is necessary to have application-independent information system which can share information description and services, and expand them easily. Thus, in this paper, we propose a semantic information system framework based on web services and ontology for Grid computing environment, called WebSIS. It makes application and middleware developer easy to build sharable and extensible information system which is easy to share information description and can provide ontology based platform-independent information services. We present efficient ontology based information system architecture through WebSIS. Discovering appropriate resource for task execution on Grid needs more high-level information processing because Grid computing environment is more complex than other traditional distributed computing environments and has various considerations which are needed for Grid task execution. Thus, we design and implement resource information system and services by using WebSIS which enables high-level information processing by ontology reasoning and semantic-matching, for automation of task execution on Grid.

• Journal of Advanced Navigation Technology
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• v.19 no.5
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• pp.423-432
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• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1064-1073
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• 2002

In this paper, we design and implement the Wireless Transaction Protocol (WTP) proposed by the Wireless Application Protocol (WAP) forum using a protocol development tool, SDL Development Tool (SDT). And we conduct a comparative performance evaluation of the WTP implementation with other three implementations that are based on different implementation models respectively: the server model, the coroutine model, and the activity-thread model. To implement WTP, we first use Unified Modeling Language (UML) for analyzing the protocol requirement and defining the protocol engine architecture. Next, we use Software Development Language (SDL) to design the protocol engine in details and then generate the WTP implementation automatically with the aid of SDT The code size of the WTP implementation generated by SDT is 62% larger than the other three implementations. However, its throughput and system response time for transaction processing is almost equal to the other three implementations when the number of concurrent clients is less than 3,000. If more than 5,000 concurrent clients tries, the transaction success rate abruptly decreases to 10% and system response time increases to 1,500㎳, due to the increased protocol processing time. But, it comes from the fact that the load overwhelms the capacity of the PC resource used in this experimentation.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.1
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• pp.56-63
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• 2016

In this study, we introduce a design of Fuzzy RBFNNs-based digit recognition system using the incremental-PCA in order to recognize the handwritten digits. The Principal Component Analysis (PCA) is a widely-adopted dimensional reduction algorithm, but it needs high computing overhead for feature extraction in case of using high dimensional images or a large amount of training data. To alleviate such problem, the incremental-PCA is proposed for the computationally efficient processing as well as the incremental learning of high dimensional data in the feature extraction stage. The architecture of Fuzzy Radial Basis Function Neural Networks (RBFNN) consists of three functional modules such as condition, conclusion, and inference part. In the condition part, the input space is partitioned with the use of fuzzy clustering realized by means of the Fuzzy C-Means (FCM) algorithm. Also, it is used instead of gaussian function to consider the characteristic of input data. In the conclusion part, connection weights are used as the extended diverse types in polynomial expression such as constant, linear, quadratic and modified quadratic. Experimental results conducted on the benchmarking MNIST handwritten digit database demonstrate the effectiveness and efficiency of the proposed digit recognition system when compared with other studies.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.237-243
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• 2007

In this paper, we propose the Real-time Dead-Pixel Detection and Compensation System for mobile camera and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However a conventional Dead-Pixel Detection Algorithm is disable to detect neighboring dead pixels and it degrades image quality by wrong detection and compensation. To detect dead pixels the proposed system is classifying dead pixels into Hot pixel and Cold pixel. Also, the proposed algorithm is processing line-detector and $5{\times}5$ window-detector consecutively. The line-detector and window-detector can search dead pixels by using one-dimensional(only horizontal) method in low frequency area and two-dimensional(vertical and diagonal) method in high frequency area, respectively. The experimental result shows that it can detect 99% of dead pixels. It was designed in Verilog hardware description language and total gate count is 23K using TSMC 0.25um ASIC library.