• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.2
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• pp.216-221
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• 2004

This paper describes an optimal synthesis method of binary neural network for pattern recognition. Our objective is to minimize the number of connections and the number of neurons in hidden layer by using a Newly Expanded and Truncated Learning Algorithm (NETLA) for the multilayered neural networks. The synthesis method in NETLA uses the Expanded Sum of Product (ESP) of the boolean expressions and is based on the multilayer perceptron. It has an ability to optimize a given binary neural network in the binary space without any iterative learning as the conventional Error Back Propagation (EBP) algorithm. Furthermore, NETLA can reduce the number of the required neurons in hidden layer and the number of connections. Therefore, this learning algorithm can speed up training for the pattern recognition problems. The superiority of NETLA to other learning algorithms is demonstrated by an practical application to the approximation problem of a circular region.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.1-7
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• 1998

High-Level synthesis of digital circuits calls for automatic translation of a behavioral description to a structural design entity represented in terms of components and connection. One of the critical steps in high-level synthesis is to determine a particular scheduling algorithm that will assign behavioral operations to control states. A new scheduling algorithm called Data Availability Scheduling (DAS) for high-level synthesis is presented. It can determine an appropriate scheduling algorithm and minimize the number of states required using data availability and dependency conditions extracted from the behavioral code, taking into account of states required using data availability and dependency conditions extracted from the behavioral code, taking into account resource constraint in each control state. The DAS algorithm is efficient because data availability conditions, and conditional and wait statements break the behavioral code into manageable pieces which are analyzed independently. The output is the number of states in a finite state machine and shows better results than those of previous algorithms.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.24-38
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• 1994

In this paper we develop the software simulator written in a C language for a frequency modulation synthesis and the approximate range of parameters, for a musically satisfactory timbre, obtained by using the software simulator will be applied to develop an algorithm for parameter extraction. For a frequency modulation synthesis, we also develop an algorithm for parameter extraction through waveform analysis in the time domain as well as spectrum analysis using a FFT in the frequency domain. To verify the validity of the developed algorithm as well as software simulator experimentally, we extract parameters for the several music instruments using the suggested algorithm and analyze the synthesized sound by applying the parameters to the software simulator. The evaluation of the synthesized sound is first done by listening the sound directly as a subjective testing. Secondly, to evaluate the synthesized sound objectively with an engineering sense, we compare the synthesized sound with an original one in a time domain and a frequency domain.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• International Journal of Contents
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• v.7 no.3
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• pp.19-28
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• 2011

This paper presents a fast and practical motion synthesis algorithm for massive number of quadruped animals. The algorithm constructs so called speed maps that contain a set of same style motions but different speed from a single cyclic motion by using IK(Inverse Kinematics) solver. Then, those speed maps are connected each other to form a motion graph. At run time, given a point trajectory that obtained from user specification or simulators, the algorithm retrieves proper speed motions from the graph, and modifies and stitches them together to create a long seamless motion in real time. Since our algorithm mainly targets on the massive quadruped animal motions, the motion graph create wide variety of different size of characters for each trajectory and automatically adjusted synthesized motions without causing artifact such as foot skating. The performance of algorithm is verified through several experiments

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.73-76
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level synthesis consist of compiling, partitioning, scheduling. In this paper, we proposed the efficient scheduling algorithm that find the number of the functional unit and scheduling into the minimum control step with silicon area resource constrained.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.141-145
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• 2009

A C-to-SystemC synthesizer which processes the input behavior according to high-level synthesis, and then transforms the synthesis result into SystemC module code is implemented in this paper. In the synthesis process, the input behavioral description in C source code is scheduled using list scheduling algorithm and register allocation is performed using left-edge algorithm on the result of scheduling. In the SystemC process, the output from high-level synthesis process is transformed into SystemC module code by combining it with SystemC features such as channels and ports. The operation of the implemented C-to-SystemC synthesizer is validated through simulating the synthesis of elliptic wave filter in SystemC code. C-to-SystemC synthesizer can be used as a part of tool-chain which helps to implement SystemC design methodology covering from modeling to synthesis.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.122-134
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• 1994

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.

• MALSORI
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• no.56
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• pp.225-235
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• 2005

Speech unit concatenation with a large database is presently the most popular method for speech synthesis. In this approach, the mismatches at the unit boundaries are unavoidable and become one of the reasons for quality degradation. This paper proposes an algorithm to reduce undesired discontinuities between the subsequent units. Optimal matching points are calculated in two steps. Firstly, the fullback-Leibler distance measurement is utilized for the spectral matching, then the unit sliding and the overlap windowing are used for the waveform matching. The proposed algorithm is implemented for the corpus-based unit concatenating Korean text-to-speech system that has an automatically labeled database. Experimental results show that our algorithm is fairly better than the raw concatenation or the overlap smoothing method.