• 전력전자학회논문지
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• 제25권6호
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• pp.477-483
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• 2020

This study proposes a DQ synchronous reference frame model of a series-parallel tuned inductive power transfer (SP-IPT) system. The wireless power transmission system experiences control difficulty because the transmitter-side controller cannot directly measure the receiver-side load voltages and currents. Therefore, a control-oriented circuit model that shows the dynamics of the IPT system is required to achieve a well-behaved controller. In this study, an equivalent circuit model of the SP-IPT system in a synchronously rotating reference frame is proposed using the single-phase DQ transformation technique. The proposed circuit model is helpful in modeling the dynamics of the voltages and currents of the transmitter- and receiver-side resonant tanks and loads. The proposed circuit model is evaluated using frequency- and time-domain simulation results.

• 전자공학회논문지
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• 제51권6호
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• pp.271-275
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• 2014

회전하는 동기 좌표계 d-q 변환을 이용한 단상 능동 전력 필터의 새로운 제어기를 제안하였다. 힐버트 변환기를 사용하여 $90{\circ}$의 위상차를 가지는 두 개의 교류 신호를 만든다. 이 신호들을 회전하는 동기 좌표계 d-q 변환을 이용하여 기본파 성분을 직류로 변환할 수 있고 따라서 고조파 검출이 용이하다. 순시 유효 전력의 평균값을 구한다. 역률 보상을 하므로 전원 전류는 전원 전압과 동위상이다. 단상에서의 전력 공식으로부터 전원 전류의 크기를 알 수 있다. 능동 전력 필터의 보상 전류의 기준 신호는 전원 전류의 기준신호에서 부하 전류를 빼주면 구할 수 있다. 새롭게 제안된 제어기에 히스테리시스 전류 제어기를 적용하여 시뮬레이션 하였다. 능동 전력 필터가 부하전류의 고조파와 무효전력을 보상하여 전원 전류가 전원전압과 동위상이 되고 전원전류가 정현파에 가깝게 되는 것을 확인하였다. 힐버트 변환기는 전대역 여파기를 사용하여 구현하였다.

• 조명전기설비학회논문지
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• 제29권12호
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• 조명전기설비학회논문지
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• 제26권1호
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• pp.29-37
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• 2012

A simple and effective dead time compensation scheme for a PWM inverter-fed permanent magnet synchronous motor (PMSM) drive using the model reference adaptive control (MRAC) and coordinate transformation is presented. The basic concept is to first transform a time-varying disturbance caused by the dead time and inverter nonlinearity into unknown constant or slowly-varying one by the coordinate transformation, and then use the MRAC design technique to estimate this parameter in the stationary reference frame. Since the MRAC scheme is a suitable way of estimating such a parameter, the control performance can be significantly improved as compared with the conventional observer-based method tracking time-varying parameters. In the proposed scheme, the disturbance voltage caused by the dead time is effectively estimated and compensated by on-line basis without any additional circuits nor existing disadvantages as in the conventional methods. The asymptotic stability is proved and the effectiveness of the proposed scheme is verified.

• Journal of Power Electronics
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• 제17권2호
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• pp.533-541
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• 2017

This paper presents a novel Parameter-Independent Fictive-Axis (PIFA) approach for the Voltage-Oriented Control (VOC) algorithm used in grid-tied single-phase inverters. VOC is based on the transformation of the single-phase grid current into the synchronous reference frame. As a result, an orthogonal current signal is needed. Traditionally, this signal has been obtained from fixed time delays, digital filters or a Hilbert transformation. Nevertheless, these solutions present stability and transient drawbacks. Recently, the Fictive Axis Emulation (FAE) VOC has emerged as an alternative for the generation of the quadrature current signal. FAE requires detailed information of the grid current filter along with its transfer function for signal creation. When the transfer function is not accurate, the direct and quadrature current components present steady-state oscillations as the fictive two-phase system becomes unbalanced. Moreover, the digital implementation of the transfer function imposes an additional computing burden on the VOC. The PIFA VOC presented in this paper, takes advantage of the reference current to create the required orthogonal current, which effectively eliminates the need for the filter transfer function. Moreover, the fictive signal amplitude and phase do not change with a frequency drift, which results in an increased reliability. This yields a fast, linear and stable system that can be installed without fine tuning. To demonstrate the good performance of the PIFA VOC, simulation and experimental results are presented.

• 전기학회논문지
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• 제64권7호
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• 전력전자학회논문지
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• 제4권3호
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• pp.275-284
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• 1999

3산 전력 시스템에서 불평형 전원의 전압은 대칭좌표법에 의하여 정상, 역상, 영상성분으로 각각 분해 될 수 있고 또한 전력 시스템에 중성선이 없는 경우 영상성분은 부하측에 나타나지 않게 된다. 따라서 중성선이 없는 불평형 시스템에서는 전원측의 역상성분만을 검출하여 보상함으로써 부하측에 평형된 전압을 공급할 수 있을 뿐만 아니라 정상성분의 크기를 제어함으로써 부하에 인가되는 전압의 크기를 조정하는 것이 가능하다. 아울러 이러한 불평형 전압에 의한 각 대칭분은 3상 2상 변환을 통한 동기좌표축상에서의 효율적인 검출이 가능한데, 본 논문에서는 전원의 불평형 성분을 동기좌표축 상에서 순시적으로 검출하여 이를 보상하고 부하의 전압조정 기능 역시 수행하는 순간전압보상기의 보상 알고리즘 및 이때 좌표변환시 필요한 전원의 위상각 정보를 전원의 정상성분에 일치시키는 새로운 위상각 검출 알고리즘을 제안한다. 제안된 보상 시스템의 성능 및 특성을 시뮬레이션을 통하여 해석하고 실험으로써 검증하였다.

• 제어로봇시스템학회논문지
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• 제9권12호
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• pp.1001-1008
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• 2003

A time-delay compensation method for vector control system is proposed that can compensate for voltage and current distortions resulting from a time delay in the overall system due to the low pass filter, hysteresis control inverter, microprocessor program computation time, and so on. The proposed scheme estimates the time delay using the difference between the Q-axis stator current command and the time-delayed actual Q-axis stator current in a synchronous reference frame, then compensates the time delay in the voltage and current using the angular displacement of a DQ transformation. Accordingly, the proposed scheme can accurately compensate for the time delay related to the overall system, thereby significantly improving the performance of the vector control system, as verified by simulation and experiment.

• Journal of Power Electronics
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• 제14권6호
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• pp.1334-1344
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• 2014

A novel single phase Phase-Locked Loop (PLL) is proposed in this paper to accurately and rapidly estimate the instantaneous phase angle of a grid. A conjugate rotating vector pair is proposed and defined to synthesize the single phase signal in the stationary reference frame. With this concept, the proposed PLL innovatively sets one phase input of the PARK transformation to a constant zero. By means of a proper cancellation, a zero steady state phase angle estimation error can be achieved, even under magnitude and frequency variations. The proposed PLL structure is presented together with guidelines for parameters adjustment. The performance of the proposed PLL is verified by comprehensive experiments. Satisfactory phase angle estimation can be achieved within one input signal cycle, and the estimation error can be totally eliminated in four input cycles for the most severe conditions.