• Journal of KIISE:Computing Practices and Letters
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• v.9 no.3
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• pp.289-300
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• 2003

Traditional kernel-level communication systems for clusters are dependent upon computing platforms. Futhermore, they are not easy to use and do not provide various functions for clusters. This paper presents an architecture and various implementation issues of a kernel-level communication system, KCCM(Kernel level Cluster Communication Module), for linux cluster. The KCCM provides asynchronous communication services as well as standard synchronous communication services using send and receive. The KCCM also automatically detects and recovers connection failures at runtime. This allows programmers to use KCCM when they build mission critical applications over TCP-based connection-oriented communication environments. Having developed using standard socket interfaces, it can be easily ported to various platforms. The experimental results show that the KCCM provides good performance for asynchronous communication patterns.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.1007-1014
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• 2003

It is important to integrate an enterprise application for automating of the business profess, which is responded by a flow of market environment. There are two categories of method that integrate enterprise applications. One is Synchronous Integration, and the other is Asynchronous Integration. EAI(Enterprise Application Integration) and Web service which of the asynchronous integration is focused in the automating method of the business process. After we construct the application integration for automating of the business process, we have to concern about managing of the business transaction. Many Organizations have proposed the process method of business transaction based on 2-phase commit protocol. But this method can′t supply the phase that classify the transaction by transaction weight. In this paper, we propose an efficient method of transaction process for business transactions, which is composed by ′Classify Phase′ that classify transactions. We called this model "3-Phase Commit Method Applied by Classify Phase", we design this model to manage an resource of enterprise efficiently. The proposed method is compared by the method based on 2-Phase commit that could be a problem of management the resource of enterprise, and the advantage of this method is certified to propose the solution of that problem.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.512-517
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• 1998

In a matrix converter, input side and output side are coupled with each other through switching elements. Since disturbances on either side affect directly on the other side, it requires a high-speed on-line control system to compensate them. We proposed in previous papers a new control strategy and an on-line control circuit for a matrix converter. The control circuit could keep the output voltage at commanded value against fluctuation in the supply voltage. Furthermore wave forms of the output voltage and the input current were always kept sinusoidal. The switching pattern was generated by comparing modified voltage references with a carrier. The carrier was synchronized with the supply voltage using a PLL system, which made the control circuit complicated and costly. This paper discusses on the possibility of an asynchronized carrier. Experiment results show the input current distortion in case of asynchronous carrier is bigger than that of synchronous carrier. However, the deterioration can be minimized by increased carrier frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.2
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• pp.71-77
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• 2019

This study proposes a circulating current reduction method that uses high-frequency voltage compensation when carrier phase difference occurs between two inverters in MSIS. In MSIS, inverters are configured in parallel to increase power capacity and to increase efficiency by using inverters only as needed. However, in the parallel inverter structure, circulating current is inevitably generated. Circulating current increases the stress on the switch, adversely affects the current control performance, and renders load sharing difficult. The proposed method compensates for the output voltage reference of the slave module by using the high-frequency voltage so that the switching pattern of each module is matched even in asynchronous carriers. The validity of the proposed method is verified by simulations and experiments with 600 W IPMSM.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.11
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• pp.4372-4394
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• 2020

The distribution of popular videos incurs a large amount of traffic at the base stations (BS) of networks. Device-to-multi-device (D2MD) communication has emerged an efficient radio access technology for offloading BS traffic in recent years. However, traditional studies have focused on synchronous user requests whereas asynchronous user requests are more common. Hence, offloading BS traffic in case of asynchronous user requests while considering their time-varying characteristics and the quality of experience (QoE) of video request users (VRUs) is a pressing problem. This paper uses social stability (SS) and video loading duration (VLD)-tolerant property to group VRUs and seed users (SUs) to offload BS traffic. We define the average amount of data transmission (AADT) to measure the network's capacity for offloading BS traffic. Based on this, we formulate a time-varying bipartite graph matching optimization problem. We decouple the problem into two subproblems which can be solved separately in terms of time and space. Then, we propose the socially aware D2MD user selection (SA-D2MD-S) algorithm based on finite horizon optimal stopping theory, and propose the SA-D2MD user matching (SA-D2MD-M) algorithm to solve the two subproblems. The results of simulations show that our algorithms outperform prevalent algorithms.

• The Journal of the Acoustical Society of Korea
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• v.39 no.3
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• pp.163-169
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• 2020

The asynchronous bistatic sonar needs to estimate direct blast arrival time at a receiver to localize targets, and therefore the direct blast arrival time estimation error could be added to target localization error in comparison with synchronous system. Direct blast especially appears as several peaks at the matched filter output by multipath, thus we compared the first peak detection technique and the maximum peak detection technique of those peaks for direct blast arrival time estimation through sea trial data. The test was performed in a shallow sea with bistatic sonar made up of spatially separated source and line array sensors. Line array sensors obtained the target signal which is generated from the echo repeater. As a result, the first peak detection technique is superior to maximum peak detection technique in direct blast arrival time estimation error. The result of this analysis will be used for further research of target tracking in the asynchronous bistatic sonar.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1423-1430
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• 2016

The MAC protocols, which are classified into synchronous and asynchronous MAC protocol in the wireless sensor network, have actively studied. Especially, the asynchronous MAC protocol needs to research on the algorithm synchronizing between nodes, since each node independently operates in its own duty cycle. Typically, Receiver-Initiated MAC protocol is the algorithm synchronizing particular nodes by using beacon immediately transmitted by each node when it wakes up. However, the sender consumes unnecessary energy because it blankly waits until receiving the receiver's beacon, even if it does not know when the receiver's beacon is transmitted. In this paper, we propose the MAC protocol which can improve the performance by selecting an optimal node between a sender and a receiver to overcome the disadvantages. The simulation results show that the proposed algorithm improves energy efficiency and decreases average delay time than the conventional algorithm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.47-55
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• 1999

In this paper, a new function hazard elimination algorithm is proposed for asynchronous circuit synthesis. In previous approach, function hazard is eliminated by using state graph which is obtained from the state assignment on STG(signal transition graph) representing transition relationship among signals. These algorithms can use conventional hazard removal and synthesis method applied in synchronous system, but it has much computational complexity and takes much time to handle the state graph. Although some hazard elimination algorithm from STG were proposed, it could not reduce the area overhead due to the addition of new signals. The proposed algorithm eliminate function hazard directly on STG and also control the number of minterms and product-term of added signal in order to minimize the area overhead. Experimental results on benchmark data shows that overall circuit area after hazard elimination is decreased about 15% on the average than that of previous method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1596-1602
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• 2021

Battery-operated IoT devices in IoT systems require low power consumption. In general, IoT devices enter a sleep state synchronously to reduce power consumption. A problem arises when an IoT device has to handle asynchronous user requests, as the duty cycle must be reduced to enhance response time. In this paper, we propose a new low-power-consumption scheme, called Repetitive Wake-up scheme for IoT systems of asynchronous environments such as indoor lights control. The proposed scheme can reduce power consumption by sending wake-up signals from the smartphone repetitively and by retaining the IoT device in sleep state to the smallest possible duty cycle. In the various environments with IoT devices at home or office space, we showed that the proposed scheme can reduce power consumption by up to five times compared to the existing synchronous interlocking technique.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.