• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2022-2028
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• 2015

SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper and faster on-board data handling in spacecraft. The standard defines timecode and its distribution which can be used for time synchronization among the nodes in a SpaceWire network. A timecode output from the time master which provides standard time over a SpaceWire network travels through links and routers to reach every nodes. While traveling, a timecode suffers from transmission delay and jitter which cause some difference in time synchronization among nodes. In this work, a simulator was developed using OMNeT++ to simulate the operation of a SpaceWire network and some analyses were performed on the transmission delay and jitter accompanied with a transmission of a timecode. The result will be used in the near future for the research of a precise time synchronization technique over a SpaceWire network.

• Journal of KIISE
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• v.42 no.1
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• pp.1-6
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• 2015

Smart electronics are now widely used in everyday life, but the size of the screen of such devices is still too small to fully enjoy multimedia content. Therefore, if the display is comprised of multiple views produced by multiple smart devices, then the screen output size can increase. However, a time delay between the devices can generate a discordance in the video and sound. This paper compares two synchronization techniques that can be used to minimize such a time delay, and proposes a synchronization technique in which, the timing of the screen for each device is calculated by synchronizing the playback time, using the timing information transferred from the control device, and periodically adjusting the playback timing forward or backward. When multimedia content is reproduced using multiple views from multiple smart devices, we can minimize the time delay, regardless of the network quality or the differences in the devices used for this technique.

• Asian-Australasian Journal of Animal Sciences
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• v.32 no.8_spc
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• pp.1284-1295
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• 2019

Considerable progress in reproduction of dairy goats has been made, with advances in reproductive technology accelerating dairy goat production since the 1980s. Reproduction in goats is described as seasonal. The onset and length of the breeding season is dependent on various factors such as breed, climate, physiological stage, male effect, breeding system, and photoperiod. The reproductive physiology of goats was investigated extensively, including hypothalamic and pituitary control of the ovary related to estrus behavior and cyclicity etc. Photoperiodic treatments coupled with the male effect allow hormone-free synchronization of ovulation, but the kidding rate is still less than for hormonal treatments. Different protocols have been developed to meet the needs and expectations of producers; dairy industries are subject to growing demands for year round production. Hormonal treatments for synchronization of estrus and ovulation in combination with artificial insemination (AI) or natural mating facilitate out-of-season breeding and the grouping of the kidding period. The AI with fresh or frozen semen has been increasingly adopted in the intensive production system, this is perhaps the most powerful tool that reproductive physiologists and geneticists have provided the dairy goat industry with for improving reproductive efficiency, genetic progress and genetic materials transportation. One of the most exciting developments in the reproduction of dairy animals is embryo transfer (ET), the so-called second generation reproductive biotechnology following AI. Multiple ovulation and ET (MOET) program in dairy goats combining with estrus synchronization (ES) and AI significantly increase annual genetic improvement by decreasing the generation interval. Based on the advances in reproduction technologies that have been utilized through experiments and investigation, this review will focus on the application of these technologies and how they can be used to promote the dairy goat research and industry development in the future.

• Journal of Digital Convergence
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• v.18 no.12
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• pp.195-204
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• 2020

The purpose of this study is to look for the relationship between export weight and control volume, inland cargo, export cargo transport, ship departure. The analysis period were used for a total of 113 monthly data from January 2011 to May 2020. Data were retrieved from the Korean Statistical Information Service of the Statistics Korea. The data used in this study were performed numerical analysis, index analysis and model analysis using the rate of change from the same month of the previous year. In the trend of the increase rate, the amount of control has plummeted from 150% to 60% due to the influence of Corona 19 in the beginning of 2020. At the same time, export weight and export cargo transport also decreased. As a result of the analysis, export weight showed relatively high synchronization with export cargo transport and control volume. On the other hand, export weight and inland cargo showed relatively low synchronization. Export weight is expected to continue in 2020 after the fluctuation rate began to decrease after 2019. If we can find the point of rebound in control volume or export cargo transport in the future, we can predict the point of increase in export weight. We expect to see an increase in export weight as soon as possible.

• International Journal of Automotive Technology
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• v.8 no.4
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• pp.467-476
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• 2007

This work verifies the chaotic motion of a steer-by-wire vehicle dynamic system, and then elucidates an application of dither smoothing to control the chaos of a vehicle model. The largest Lyapunov exponent is estimated from the synchronization to identify periodic and chaotic motions. Then, a bifurcation diagram reveals complex nonlinear behaviors over a range of parameter values. Finally, a method for controlling a chaotic vehicle dynamic system is proposed. This method involves applying another external input, called a dither signal, to the system. The designed controller is demonstrated to work quite well for nonlinear systems in achieving robust stability and protecting the vehicle from slip or spin. Some simulation results are presented to establish the feasibility of the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.4
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• pp.369-378
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• 1992

This paper proposes a utility parallel processing inverter system, which consists of a voltage source PWM inverter, isolation transformer and a reactor linking the inverter to utility line. This system realizes following functions : (1) voltage phase frequency and amplitude synchronization between inverter and utility line at stand-alone mode. (2) current phase synchronization between inverter and load at parallel mode. Therefore, despite sudden increase in load current over setting point at stand-alone mode, inverter system can be transferred into parallel mode immediately without transient current. Furthermore, high frequency(18KHz) PWM control and sinusoidal filtering improve the inverter output waveform by eliminating high order harmonic components as well as low order. As a switching device, IGBT is used for high frequency switching and large current capacity.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.26-33
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• 1992

This paper describes a new phase-difference detection method and the associate process algorithm for calculating the mean value of phase difference detected and OVCXO control value and for monitoring and controlling the DP-PLL operation status to be used in the design of a high-frequency DP-PLL. Through the experiments of DP-PLL implemented with 16-bit processor, memories, pheriperals and OVCXO to eraluate the suggested method and algorithm, it is shown that a remarkable improvement in PLL function such as phase detection, and reference clock tracing capability, jitter absorbability and frequency stability compared with other existing DP-PLL synchronization device is achieved.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.40-47
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• 1998

This paper presents the physiological signal processing CMOS one chip for transmitting human bodys small electrical signals such as electrocardiogram(EKG) or electromyogram(EMG) and the external system for receiving signals was implemented by the commercial ICs. For simultaneous four-subject four-channel telemetry, a new enfored synchronization techniqeu using infrared bi-directional communication has been proposed. The telemeter IC with the size of 5.1*5.1mm$^{2}$ has the following functions: receiving of command signal, initialization of internal state of all functional blocks, decoding of subject-selection signal, time multiplexing of 4-channel modulated physiological signals, transmitting of telemetry signal to external system and auto power down control. The newly designed synchronized oscillator with low supply voltage dependence in the telemeter IC operates at a supply voltage from 4.6~6.0V and the nonlinearity error of PIM modulator was less than 1.2%F.S(full scale). The power saving block operates at the period of 2.5ms even if the telemetry IC does not receive command signal from external system for a constant time.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.281-285
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• 1990

Our N.C. sewing machine is a device that acts sewing automatically in reference to N.C. data made by data input device. Our N.C. sewing mechine is composed of induction motor that has electric clutch and brake, step motor that drives x-y table. Sewing area of our machine is 170 mm * 100 mm, maximum sewing speed is about 2000 spm, maximum stitch length 6.2 mm. In actual sewing, synchronization between motion of needle up-down and motion of x-y table is a critical factor. In this paper, technology about synchronization will be profoundly discussed.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.634-638
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• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.