• Title/Summary/Keyword: Symbol Offset

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Implementation of Timing Synchronization in Vehicle Communication System

  • Lee, Sang-Yub;Lee, Chul-Dong;Kwak, Jae-Min
    • Journal of information and communication convergence engineering
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    • v.8 no.3
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    • pp.289-294
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    • 2010
  • In the vehicle communication system, transferred information is needed to be detected as possible as fast in order to inform car status located in front and rear side. Through the moving vehicle information, we can avoid the crash caused by sudden break of front one or acquire to real time traffic data to check the detour road. To be connecting the wireless communication between the vehicles, fast timing synchronization can be a key factor. Finding out the sync point fast is able to have more marginal time to compensate the distorted signals caused by channel variance. Thus, we introduce the combination method which helps find out the start of frame quickly. It is executed by auto-correlation and cross-correlation simultaneously using only short preambles. With taking the absolute value at the implemented synch block output, the proposed method shows much better system performance to us.

16-QAM-Based Highly Spectral-Efficient E-band Communication System with Bit Rate up to 10 Gbps

  • Kang, Min-Soo;Kim, Bong-Su;Kim, Kwang Seon;Byun, Woo-Jin;Park, Hyung Chul
    • ETRI Journal
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    • v.34 no.5
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    • pp.649-654
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    • 2012
  • This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

On the Design of Demodulator and Equalizer of 9600 BPS Modem (9600 BPS Modem의 복조기와 Equalizer에 관한 연구)

  • 장춘서;은종관
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.20 no.4
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    • pp.10-15
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    • 1983
  • In this paper effective methods of demodulation and equalization in a 9600 bps modem have been studied. To reduce the number of multiplications required per symbol in demodula-tion, the method of using a decimation filter is presented. In the equalizer the optimum step size and the steady state mean-squared error (MSE) are obtained from computer simulation results. The performance of the first-order carrier phase tracking loop is compared with that of the second-order loop when carrier frequency offset exists. In addition, the finite word length effects in the equalizer are studied.

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A new spect of offset and step size on BER perfermance in soft quantization Viterbi receiver (연성판정 비터비 복호기의 최적 BER 성능을 위한 오프셋 크기와 양자화 간격에 관한 성능 분석)

  • Choi, Eun-Young;Jeong, In-Tak;Song, Sang-Seb
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.1A
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    • pp.26-34
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    • 2002
  • Mobile telecommunication systems such as IS-95 and IMT-2000 employ frame based communication using frames up to 20 msec in length and the receiving end has to store the whole frome before it is being processed. The size of the frame buffer ofter dominates those of the processing unit such as soft decision Viterbi decoder. The frame buffer for IMT-2000, for example, has to be increased 80 times as large as that of IS-95. One of the parameters deciding the number of bits in a frame will be obviously the number of bits in soft quantization. Start after striking space key 2 times. This paper has studied a new aspect of offset and quantization step size on BER performance and proposes a new 3-bit soft quantization algorithm which shows similar performance as that of 4-bit soft decision Viterbi receiver. The optimal offset values and step sizes for the other practical quantization levels ---16, 8, 4, 2--- have also been found. In addition, a new optimal symbol metric table has been devised which takes the accumulation value of various repeated signals and produces a rescaled 3-bit valu.tart after striking space key 2 times.

A Robust Decorrelating Multiuser Detector for Asynchronous DS/CDMA Communication Systems (비동기 DS/CDMA 시스템을 위한 역상관 다중사용자 검출기)

  • Yoon, Seok-Hyun;Lee, Kyung-Ha;Hong, Kwang-Seok
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.6
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    • pp.1-8
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    • 1998
  • This paper presents an asynchronous DS/CDMA multiuser detector, which is a two stage, symbol-by-symbol scheme consisting of conventional detectors followed by linear decorrelating detectors. The conventional detector first makes temporal decisions and the detected symbols are delayed by one symbol period to be used for the selection of decorrelating bases in the subsequent decorrelaing detection stage. It also employs a bank of early-late correlators in place of a bank of single correlators taking the small offset of chip timing asynchronism into account. The proposed detector requires only the coarse knowledge of relative time delays of interfering users and is suitable for digital implementation. To verify the detector performance, the analytical BER performance will be given and compared with the simulation results for BPSK DS/CDMA signals in AWGN channel. While the performance of the proposed detector will be analyzed for time-limited signal, the simulation is carried out for both the time-limited and band-limited signals. As can be seen in the simulation results, the proposed scheme shows good results.

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Performance Improvement of MCMA Equalizer with Parallel Structure (병렬 구조를 갖는 MCMA 등화기의 성능 개선)

  • Yoon, Jae-Sun;Lim, Seung-Gag
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.11 no.5
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    • pp.27-33
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    • 2011
  • In digital communication system that the Modified Constant Modulus Algorithm (MCMA) reduced the use of the adaptive equalization algorithm to combat the Inter-symbol Interference (ISI). MCMA is relatively brief operation. The major point of MCMA that it only achieves moderate convergence rate and steady state mean square error (MSE). In this paper suggest, MCMA equalization improve the performance with parallel structure. It combines Modified Constant Modulus Algorithm(MCMA) and Modified Decision Directed(MDD) algorithm. By exploiting the inherent structural relationship between the 4-QAM signal's coordinates and 16-QAM signal's coordinates, another style of cost function for Modified Constant Modulus Algorithm(MCMA) is defined and If it happen to offset of received signals and MCMA is poor performance in order to overcome this because the paper combines apply for MCMA and MDD(Modified Decision Direct) algorithm. By computer simulation, we confirmed that the proposed PMCMA-MDD algorithm has the fater convergence rate and steady mean square error than the conventional MCMA.

A Symbol Timing Recovery scheme using the jitter mean of adaptive loop filter in ATSC DTV systems (적응적 루프필터의 지터 평균값을 이용한 ATSC DTV 심볼 타이밍 동기 방식)

  • Kim, Joo-Kyoung;Lee, Joo-hyoung;Song, Hyun-keun;Kim, Jae-Moung;Kim, Seung-Won
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.10 s.340
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    • pp.1-8
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    • 2005
  • This Paper Proposes the algorithm for improving the Performance or symbol timing synchronization in hoc terrestrial DTV system. The Gardner algerian is used for symbol timing synchronization has good performance in multipath fading environment but degradation of performance is caused by jitter. Though the amount of jitter becomes more little as narrow bandwidth of loop Inter, convergence speed becomes slower. This paper propose the algorithm that averages out values of loop filter every certain time and gradually reduces the bandwidth of loop filter after estimating offset using this average for the high speed of convergence and reducing the met of jitter. The proposed algorithm has better performance with high speed of convergence and the amount of jitter than conventional method.

An Enhanced Scheme with CFO and SFO in OFDMA system (OFDMA 시스템에서 SFO와 CFO 저감 기법에 관한 연구)

  • Lee, Young-Gwang;Lee, Kyu-Seop;Choi, Gin-Kyu
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.1
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    • pp.1-6
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    • 2014
  • Recently, orthogonal frequency-division multiplexing(OFDM), with clusters of subcarriers allocated to different subscribers(often referred to as OFDMA), has gained much attention for its ability in enabling multiple-access wireless multimedia communications. In such systems, carrier frequency offsets (CFOs) can destroy the orthogonality among subcarriers. And the mismatch in sampling frequencies between transmitter and receiver can lead to serious degradation due to the loss of orthogonality between the subcarriers. As a result, multiuser interference (MUI) along with significant performance degradation can be induced. In this paper, we present a scheme to compensate for the SFOs and CFOs at the base station of an OFDMA system. A novel sampling frequency offset estimation algorithm is proposed, which is based on the repetition of a symbol at the communication start-up. Then, circular convolutions are employed to generate the interference after the discrete Fourier transform processing, which is then removed from the original received signal to increase the signal to interference power ratio(SIR). Simulation result shows that the proposed scheme can improve system performance.

An Efficient Receiver Structure Based on PN Performance in Underwater Acoustic Communications (수중음향통신에서 PN 성능 기반의 효율적인 수신 구조)

  • Baek, Chang-Uk;Jung, Ji-Won
    • Journal of Navigation and Port Research
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    • v.41 no.4
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    • pp.173-180
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    • 2017
  • Underwater communications are degraded as a result of inter symbol interference in multipath channels. Therefore, a channel coding scheme is essential for underwater communications. Packets consist of a PN sequence and a data field, and the uncoded PN sequence is used to estimate the frequency and phase offset using a Doppler and phase estimation algorithm. The estimated frequency and phase offset are fed to a coded data field to compensate for the Doppler and phase offset. The PN sequence is generally utilized to acquire the synchronization information, and the bit error rate of an uncoded PN sequence predicts the performance of the coded data field. To ensure few errors, we resort to powerful BCJR decoding algorithms of convolutional codes with rates of 1/2, 2/3, and 3/4. We use this powerful channel coding algorithm to present an efficient receiver structure based on the relation between the bit error of the uncoded PN sequence and coded data field in computer simulations and lake experiments.

Design of an Efficient Initial Frequency Estimator based on Data-Aided algorithm for DVB-S2 system (데이터 도움 방식의 효율적인 디지털 위성 방송 초기 주파수 추정회로 설계)

  • Park, Jang-Woong;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.3A
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    • pp.265-271
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    • 2009
  • This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.