• Title/Summary/Keyword: Switching algorithm

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Finite Control Set Model Predictive Current Control for a Cascaded Multilevel Inverter

  • Razia Sultana, W.;Sahoo, Sarat Kumar
    • Journal of Electrical Engineering and Technology
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    • v.11 no.6
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    • pp.1674-1683
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    • 2016
  • In this paper, a Finite Control Set Model Predictive Control (FCS-MPC) for a five level cascaded multilevel inverter (CMLI) with reduced switch topology is proposed. Five switches are used here instead of conventionally used eight switches. The main contribution of this paper is to make the MPC controller work for the reduced switch topology using only 19 voltage vectors in place of conventional 61 voltage vectors for a five level CMLI. This simplifies the execution of the MPC algorithm, paving a way for the significant reduction in the computational time. The controller makes use of the excellent ability of MPC to multitask, by adding one more objective which is to reduce the average switching frequency in addition to controlling the load current. This is especially important, since switching losses and therefore switching frequency is significant for high-power applications. The trade-off of this MPC is that the current is not as smooth as the 61 vector scheme, but well within the limits of IEEE standards. The results shown prove that this MPC works well in steady state and dynamic conditions too.

A Modularized Equalizer for Supercapacitor Strings in Hybrid Energy Storage Systems

  • Gao, Zhigang;Jiang, Fenlin
    • Journal of Power Electronics
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    • v.16 no.4
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    • pp.1469-1482
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    • 2016
  • In hybrid energy storage systems, supercapacitors are usually connected in series to meet the required voltage levels. Equalizers are effective in prolonging the life of hybrid energy storage systems because they eliminate the voltage imbalance on cells. This study proposes a modularized equalizer, which is based on a combination of a half-bridge inverter, an inductor, and two auxiliary capacitors. The proposed equalizer inherits the advantages of inductor-based equalization systems, but it also offers unique merits, such as low switching losses and an easy-to-use control algorithm. The zero-voltage switching scheme is analyzed, and the power model is established. A fixed-frequency operation strategy is proposed to simplify the control and lower the cost. The switching patterns and conditions for zero-voltage switching are discussed. Simulation results based on PSIM are presented to verify the validity of the proposed equalizer. An equalization test for two supercapacitor cells is performed. An experimental hybrid energy storage system, which consists of batteries and supercapacitors, is established to verify the performance of the proposed equalizer. The analysis, simulation results, and experimental results are in good agreement, thus indicating that the circuit is practical.

Switching Element-Disjoint Multicast Scheduling for Avoiding Crosstalk in Photonic Banyan-Type Switching Networks (Part II):Scheduling Lengths and Nonblocking Property (광 베니언-유형 교환 망에서의 누화를 회피하기 위한 교환소자를 달리하는 멀티캐스트 스케줄링(제2부):스케줄링 길이 및 넌블럭킹 특성)

  • Tscha, Yeong-Hwan
    • Journal of KIISE:Information Networking
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    • v.28 no.4
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    • pp.657-664
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    • 2001
  • In our predecessor paper(Part I)[13], we introduced a graph that represents the crosstalk relationship among multicast connections in the photonic Banyan-type switching network, and found the upper bound on the degree of it. In this paper(Part II), we consider the number of routing rounds(i.e., scheduling length) required for SE(switching element)-disjoint multicasting in photonic Banyan-type switching networks. Unfortunately, the problem to find an optimal scheduling length is NP-complete thus, we propose an approximation algorithm that gives its scheduling length is always within double of the upper bound on the optimal length. We also study the scheduling length on the Iink-disjoint(i.e., nonblocking) multicasting. Various nonblocking Banyan-type multicasting networks are found under the scheduling lengths.

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Identity Based Proxy Re-encryption Scheme under LWE

  • Yin, Wei;Wen, Qiaoyan;Li, Wenmin;Zhang, Hua;Jin, Zheng Ping
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.12
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    • pp.6116-6132
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    • 2017
  • The proxy re-encryption allows an intermediate proxy to convert a ciphertext for Alice into a ciphertext for Bob without seeing the original message and leaking out relevant information. Unlike many prior identity based proxy re-encryption schemes which are based on the number theoretic assumptions such as large integer factorization and discrete logarithm problem. In this paper, we first propose a novel identity based proxy re-encryption scheme which is based on the hardness of standard Learning With Error(LWE) problem and is CPA secure in the standard model. This scheme can be reduced to the worst-case lattice hard problem that is able to resist attacks from quantum algorithm. The key step in our construction is that the challenger how to answer the private query under a known trapdoor matrix. Our scheme enjoys properties of the non-interactivity, unidirectionality, anonymous and so on. In this paper, we utilize primitives include G-trapdoor for lattice and sample algorithms to realize simple and efficient re-encryption.

The study on the distribute type liner encoder (분배용 선형 엔코더의 개발)

  • Park, Hyun-Ju;Park, Sung-Jun;Kim, Jong-Dal;Shon, Mu-Heon;Kim, Gyu-Seob;Lee, Yil-Chun
    • Proceedings of the KIEE Conference
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    • 2001.07e
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    • pp.127-133
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    • 2001
  • In SRM drive, the ON OFF angles of each phase switch should be accurately controlled in order to control the torque and speed stably. The accuracy of the switching angles is dependent upon the resolution of the encoder and the sampling period of the microprocessor, that are used to provide the information of the rotor position and to control the SRM power circuit, respectively. However, as the speed increases, the amount of the switching angle deviation from the preset values is also increased. Therefore, the low cost encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using the simple digital logic circuit is also presented in this paper. As a result, a stable high speed SRM drive can be achieved by the high resolution switching angle control and it is verified from the experiments that the proposed encoder and logic controller can be a powerful candidate for the practical low cost SRM drive.

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Optimized Design of Bi-Directional Dual Active Bridge Converter for Low-Voltage Battery Charger

  • Jeong, Dong-Keun;Ryu, Myung-Hyo;Kim, Heung-Geun;Kim, Hee-Je
    • Journal of Power Electronics
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    • v.14 no.3
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    • pp.468-477
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    • 2014
  • This study proposes an optimized design of a dual active bridge converter for a low-voltage charger in a military uninterrupted power supply (UPS) system. The dual active bridge converter is among various bi-directional DC/DC converters that possess a high-efficiency isolated bi-directional converter. In the general design, the zero-voltage switching(ZVS) region is reduced when the battery voltage is high. By contrast, efficiency is low because of high conduction losses when the battery voltage is low. Variable switching frequency is applied to increase the ZVS region and the power conversion efficiency, depending on battery voltage changes. At the same duty, the same power is obtained regardless of the battery voltage using the variable switching frequency. The proposed method is applied to a 5 kW prototype dual active bridge converter, and the experimental results are analyzed and verified.

Synchronization Strategy of the Points of Turn-Off Time Using the Miller Effect on Connecting the Semiconductor Devices in Series (전력용 반도체 소자의 직렬연결시 밀러효과를 이용한 소호시점 동기화 전략)

  • Sim, Eun-Yong;Seo, Beom-Seok;Hyun, Dong-Seok
    • Proceedings of the KIEE Conference
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    • 1991.07a
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    • pp.596-599
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    • 1991
  • This paper describes a novel switching algorithm of series connected power semiconductors for high voltage applications. In order to improve the reliability and efficiency of high voltage static power converters, we study on the switching characteristics of series connected power semiconductors and then propose "a servo control of snubber capacitor value" for the dynamic voltage balancing under turn-off state in series connected power semiconductors. Finally, we illustrate the validity of this algorithm by computer simulation and experimental results.

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Development of the Small-displacement-movement of a Pneumatic piston and the Hybrid Control Algorithm for Precision Position Control (정밀 위치제어를 위한 공압 피스톤의 미소변위 이송방법 및 혼합 제어 알고리즘 개발)

  • Roh, Chul-Ha;Kim, Yeung-Shik
    • Journal of the Korean Society for Precision Engineering
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    • v.18 no.7
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    • pp.40-45
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    • 2001
  • This paper proposes a methodology for the small-displacement-movement of a piston and develops a hybrid control algorithm for the precision position control of a pneumatic rodless cylinder. The pneumatic system uses the voltage-proportional solenoid valves to minimum valve switching since the on/off type valves are create diffculties for accurate position control and induce a lot of valve switching. For the accurate position control a methodology for the small-displacement-movement of the piston is developed and identified experimentally. The main consideration on the development of the hybrid control law is to eliminate a stick-slip phenomenon in the pneumatic control system. This paper addresses these critical issues and presents experimental results for the pneumatic control system.

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Recirculating Shuffle-Exchange Interconnection ATM Switching Network Based on a Priority Control Algorithm (우선순위 제어기법을 기반으로 한 재순환 Shuffle-Exchage 상호연결 ATM 스위치)

  • Park, Byeong-Su
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.6
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    • pp.1949-1955
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    • 2000
  • This paper proposes a multistage interconnection ATM switching network without internal blocking. The first is recirculating shuffle-exchange network improved on hardware complexity. The next is connected to Rank network with tree structure. In this network, after the packets transferred to the same output ports are given each priority, only a packet with highest priority is sent to the next, an the others are recirculated to the first. Rearrangeability through decomposition and composition algorithm is applied for the transferred packets in hanyan network and all they arrive at a final destinations. To analyze throughput, waiting time and packet loss ratio according tothe size of buffer, the probabilities are modeled by a binomial distribution of packet arrival.

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A Test Vector Reordering for Switching Activity Reduction During Test Operation Considering Fanout (테스트시 스위칭 감소를 위해 팬 아웃을 고려한 테스트벡터 재 정렬)

  • Lee, Jae-Hoon;Baek, Chul-Ki;Kim, In-Soo;Min, Hyoung-Bok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.5
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    • pp.1043-1048
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    • 2011
  • Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption.