• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.4
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• pp.105-109
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• 2018

In this paper, the performance enhancement of a time-modulated array is described. The proposed time-modulated array is based on the topology of a conventional array but uses apodized discrete time switching, instead of phase shifters, to achieve beamforming functions with side-band suppression. Numerical simulations are carried out to examine the performance of this beamforming system based on apodized time sequence of 16 elements linear array. Numerical results reveal that the proposed method provides a more flexible and accurate way of producing desired beampatterns with low or ultralow side-lobe level (SLL) compared with the conventional methods.

• Cross-Cultural Studies
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• v.37
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• pp.361-382
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• 2014

This study aims to investigate the change of functions of duibuqi and analysis other fuctions of duibuqi apart from apology from pragmatics and conversation analysis perspectives. Duibuqi consists of dui(face) and buqi(be not capable of performing), and means 'be not capable of facing'. After that, it is assumed to have changed to 'ashamed' and finally 'sorry'. In terms of functions, duibuqi is generally regarded as meaning 'sorry' typically, so mei guanxi is considered to consist adjacency pair with it, but in this investigation, mei guanxi is very little adjacent to duibuqi contrary to expectation(n=2/28, per.=7.1/100). About half of duibuqi(n=15/28, per.=53.6/100) functions in apology action sequence, and in the sequence, duibuqi functions much more for take the lead in apology(n=11/15) but not for a reaction against scolding(n=4/15). And the other half of duibuqi(n=13/28, per.=46.4/100) functions for softening the impact of reject or direct action, or for switching situations, e.g. from favorable situation to unfavorable situation, or for expressing speaker's emotion to the other's repair etc. Consequently, duibuqi has being changed its meanings and its functions is being changed accordingly.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1027-1036
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• 2018

In this paper a new generalized space vector pulse width modulation scheme is proposed based on the principle of reverse mapping to drive the switches of multilevel inverters. This projected scheme is developed based on the middle vector of the subhexagon which holds the tip of the reference vector, which plays a major role in mapping the reference vector. A new approach is offered to produce middle vector of the subhexagon which holds tip of the reference vector in the multilevel space vector plane. By using middle vector of the subhexagon, reference vector is linked towards the inner two level sub-hexagon. Then switching vectors, switching sequence and dwell times corresponding to a particular sector of a two-level inverter are determined. After that, by using the two level stage findings, the switching vectors related to exact position of the reference vector are directly generated based on principle of the reverse mapping approach and do not need to be found at n level stage. In the reverse mapping principle, the middle vector of subhexagon is added to the formerly found two level switching vectors. The proposed generalized algorithm is efficient and it can be applied to an inverter of any level. In this paper, the proposed scheme is explained for a five-level inverter and the performance is analyzed for five level and three level inverters through MATLAB. The simulation results are validated by implementing the propose scheme on a V/f controlled three-level inverter fed induction motor using dSPACE control desk.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.134-140
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.4
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• pp.22-32
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• 2001

In this paper, we propose an average acquisition time and hardware design of high speed PN code synchronous acquisition system using DMF(Digital Matched Filter) with new switching method in DS-SS/CDMA(Direct Sequence Spread Spectrum Code Division Multiple Access). In reality, the PN code synchronous acquisition system using DMF has very complicated hardware, high cost and high power consumption. The PN code synchronous acquisition system using proposed switching method DMF can overcome those disadvantages. Therefore, we can make hardware simple and obtain low power and high density by reducing the area by 1/5 against the conventional approaches of using either the matched filters or the serial correlators. The proposed system architecture is also simple and easily controllable since there is no square-term circuit after execution of digital filtering.

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.5
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• pp.25-36
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• 2022

This paper proposes a random sign reversal technique in space frequency block code for single carrier modulation. The traditional space time and frequency block coding technique may be confronted with radio environments openly, severe radio hijacking problems are to be overcome. In order to avoid such an open radio issue, random coded data protection technique for space-time block code was proposed, but this algorithm can change channel combination per an Orthogonal Frequency Division Multiplexing block. This kind of slow switching increases the probability that nearby receivers will detect the transmitted data. This paper proposes a fast switching algorithm per data symbols' basis which is a random sign reversal technique in space frequency block code for Single Carrier Modulation. It is shown in simulation that the proposed one has a superior performance in comparison with the performance of the receiver which do not know the random timing sequence of sign reversal.

• ETRI Journal
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• v.18 no.4
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• pp.265-286
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• 1997

This paper presents a new software development environment that supports an integrated methodology for covering all phases of software development and gives integrated methods with tools for ITUT (Telecommunication Standardization Section of the International Telecommunication Union) languages. The design of the environment to improve software productivity and quality is based on five main concepts: 1) formal specifications based on SDL (Specification and Description Language) and MSC (Message Sequence Charts) in the design phase, 2) verification and validation of those designs by tools, 3) automatic code generation and a safe separate compilation scheme based on CHILL (CCITT High-Level Language) to facilitate programming-in-the-many and programming-in-the-large. 4) debugging of distributed real-time concurrent CHILL programs, and 5) simulation of application software for integrated testing on the host machine based on CHILL. The application results of the environment compared with other approaches show that the productivity is increased by 19 % because of decreasing implementation and testing cost, and the quality is increased by 83 % because of the formal specifications with its static and dynamic checking facilities.

• Journal of Power Electronics
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• v.13 no.4
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• pp.558-568
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• 2013

In this paper, a new decoupling technique for a flyback inverter using an active power decoupling circuit with auxiliary winding and a novel switching pattern is proposed. The conventional passive power decoupling method is applied to control Maximum Power Point Tracking (MPPT) efficiently by attenuating double frequency power pulsation on the photovoltaic (PV) side. In this case, decoupling capacitor for a flyback inverter is essentially required large electrolytic capacitor of milli-farads. However using the electrolytic capacitor have problems of bulky size and short life-span. Because this electrolytic capacitor is strongly concerned with the life-span of an AC module system, an active power decoupling circuit to minimize input capacitance is needed. In the proposed topology, auxiliary winding defined as a Ripple port will partially cover difference between a PV power and an AC Power. Since input capacitor and auxiliary capacitor is reduced by Ripple port, it can be replaced by a film capacitor. To perform the operation of charging/discharging decoupling capacitor $C_x$, a novel switching sequence is also proposed. The proposed topology is verified by design analysis, simulation and experimental results.

• Journal of the Korea Computer Industry Society
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• v.3 no.2
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• pp.149-158
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• 2002

This paper deals with design and verification of an arithmetic logic unit(ALU) to be used for development of optical computers. The ALU is based on optical switching device, $LiNbO_3$, which is easy to interface with electronic technology and most common in the market. It consists of an arithmetic/logic circuit performing logic operations, memory devices storing operands and the results of operations, and supplementary circuits to select instruction codes, and operates in bit-serial manner. In addition, a simulator is developed for verification of the design, and a set of basic instructions are executed in sequence and step-by-step changes in the accumulator and the memory are examined through simulations, to show that various operations are performed correctly.