• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.230-237
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• 2013

This paper presents a novel nonlinear model of Switched Reluctance Generator (SRG) based on wind Energy Conversion system. Closed loop control with based Proportional Integrator current Chopping Control machine model is used. A Power converter in SRG can be controlled by using PI-CCC proposed model, and can be produced maximum power efficiency and minimize the ripple contents in the output of SRG. A second power converter namely PI based controlled PWM Inverter is used to interface the machine to the Grid. An effective control technique for the inverter, based on the pulse width modulation (PWM) scheme, has been developed to make the line voltage needs less power switching devices and each pair of turbine the generated active power starts increasing smoothly. This proposed control scheme feasibility and validity are simulated on SIMULINK/SIM POWER SYSTEMS only.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• Journal of Sensor Science and Technology
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• v.31 no.2
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• pp.115-119
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• 2022

A readout circuit for a mercury-cadmium-telluride (MCT)-amplified mid-wave infrared (IR) photodetector was realized and applied to noncontact chemical agent detectors based on a quantum cascade laser (QCL). The QCL emitted 250 times for each wavelength in 0.2-㎛ steps from 8 to 12 ㎛ with a frequency of 100 kHz and duty ratio of 10%. Because of the nonconstant QCL emission power during on-duty, averaging the photodetector signals is essential. Averaging can be performed in digital back-end processing through a high-speed analog-to-digital converter (ADC) or in analog front-end processing through an integrator circuit. In addition, it should be considered that the 250 IR data points should be completely transferred to a PC during each wavelength tuning period of the QCL. To average and minimize the IR data, we designed a readout circuit using the analog front-end processing method. The proposed readout circuit consisted of a switched-capacitor integrator, voltage level shifter, relatively low-speed analog-to-digital converter, and micro-control unit. We confirmed that the MCT photodetector signal according to the QCL source can be accurately read and transferred to the PC without omissions.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.10 no.3
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• pp.237-242
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• 2016

The major advantage of slip-ring technology in Spiral CT is that it facilitates continuous rotation of the x-ray tube, so that volume data can be acquired from a patient quickly. Not only for such a fast scan, but also for the dose reduction purpose, high signal-to-noise ratio and fast data acquisition system is required. In this study, we have built a multi-channel photodetector and multi-channel data acquisition system for CT application. The detector module consisted of CdWO4 crystal and Si photodiode in 16 channels. For the performance test of the preamplifier stage, both the transimpedance and switched integrator types are optimized for the photodetector modules. Switched integrator showed better noise performance in the limited bandwidth which is suitable for the current CT application. The control sequence for data acquisition and 20 bit ADC is designed with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and implemented on FPGA(Field Programmable Gate Array) chip. Our Si photodiode detector module coupled to CdWO4 crystal showed comparable signal with other commercially available photodiode for CT. Switched integrator type showed higher SNR but narrower bandwidth compared to transimpedance preamplifier. Digital hardware is designed by FPGA, so that the control signal could be redesigned without hardware alteration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.50-55
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• 2011

In this paper, Intermediate frequency tunable 4th order Switched Capacitor(SC) bandpass Sigma-Delta(${\Sigma}-{\Delta}$) modulator using feedback integrator using feedback integrator coefficients is proposed. The center frequency of the modulator can be easily changed than conventional structure because of a number of integrator coefficients which is decided rate of capacitors in circuit is reduced. In addition additive clocks and additive clock generating circuit are not necessary. The purposed modulator was implemented in $0.18{\mu}m$ CMOS technology. The resolution of the modulator within 200 kHz bandwidth and 80 MHz sampling frequency under fin = 15 MHz, 20 MHz, 25 MHz are over 12 bit.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.12
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• pp.691-699
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• 2004

SRM(Switched Reluctance Motor) drives require the accurate position information of the rotor. These informations are generally provided by a tacho generator or digital shaft-position encoder These speed sensors lower the system reliability and require special attention to noise. This paper describes a new approach to estimating SRM speed from measured terminal voltages and currents for speed sensorless control. The described method is based on the sliding mode observer. The rotor speed and position observers are estimated by the adaptation law using the real and estimated currents. However, the conventional adaptive sliding mode observer based on the variable structure control theory has some disadvantages that the estimated values including the high-frequency chattering and the steady state error generated due to the infinite feedback gain chosen and the discontinuous control input. To reduce the chattering and steady state error, an integrator is also inserted in the sliding mode observer strategy. The described adaptive sliding mode observer decreases the vibration to the switching hyper-plane of the sliding mode by adding integrator. The described methodology incorporates the Lyapunov algorithm to drive the rotor speed and the stator resistance such that it can overcome the problem of sensitivity in the face of SRM parameter variation. Also, without any mechanical information. The rotor speed of SRM is obtained form adaptive scheme. The described method is verified through the simulation and experiment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.103-105
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• 2002

Instantaneous following PWM control technique is pulsed nonlinear dynamic control method. This new control technique using analog integrator is proposed to control the duty ratio D of Cuk converter. In this control method, the duty ratio of a switch is exactly equal to or proportional to the control reference in the steady state or in a transient. Proposed control method compensates power source perturbation in one switching cycle, and the average value of the dynamic reference in one switching cycle. There is no steady state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with Cuk converter have demonstrated the robustness of the control method and verified theoretical prediction. The control method is very general and applicable to all type PWM.

• Journal of Industrial Technology
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• v.16
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• pp.191-195
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• 1996

This paper deals with the tapped time delay circuit with SCF(Switched Capacitor Filters). This filter is composed of lossless discrete integrator and the SCF has 2-phase clocks. Experimental results have shown that telephone signals (0~4kHz) could be delayed in the range of sampling frequency 80kHz. But above the range, operational amplifiers and analog switchs have been difficult in the normal operating condition.

• Journal of Power Electronics
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• v.17 no.3
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• pp.798-810
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• 2017

This paper presents a combined system of a small-capacity inverter and multigroup delta-connected thyristor switched capacitors (TSCs). The system is referred to as a hybrid static compensator (HSC) and has the functions of dynamic reactive power compensation and harmonic suppression. In the proposed topology, the load reactive power is mainly compensated by the TSCs. Meanwhile the inverter is meant to cooperate with TSCs to achieve continuous reactive power compensation, and to filter the harmonics generated by nonlinear loads and the TSCs. First, the structure and mathematical model of the HSC are discussed Then the control method of the HSC is presented. An improved reduced order generalized integrator (ROGI)-based selective current control method is adopted in the inverter to achieve high-performance reactive and harmonic current compensation. Meanwhile, a switch control strategy is proposed to implement precise and fast switching of the TSCs and to avoid changing the time delay needed by the conventional switch strategy. Experiments are implemented on a 20 KVA HSC prototype and the obtained results verify the validity of the proposed HSC system.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.