• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.115-123
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• 2002

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter. The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms. The Proposed switch acquires control over priority transmission through the REQ signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the Proposed switch under uniform traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.11 no.1 s.39
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• pp.157-165
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• 2006

This paper proposes a new output-buffered multicast ATM switch with tandem crosspoints switching fabric, named the MTCOS(Multicast Tandem Crosspoint Output-buffered Switch). The MTCOS consists of multiple simple crosspoint switch fabrics, named TCSF(Tandem Crosspoint Switch Fabric) , and concentrated output buffers for efficient multicasting. The TCSF resolves the cell delay deviation problem which the self-routing crossbar switches inherently have. Further, it offers multiple concurrent pathes from one input to multiple output ports. It also provides multi-channel switching by easy software configuration and has several desirable characteristics such as scalability, high Performance, and modularity. A shared traffic concentration and output queuing strategies of the MTCOS results in lower cell loss as well as lower cell delay time over a wide range of multicast traffic. Furthermore, it has lower hardware complexity than that of the SCOQ and Knockout multicast switch to achieve the same Knockout concentration rate as the conventional switches. It is shown that the proposed switch can be easily applied to design high performance for any multicast traffic by analytic analysis and computer simulation.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.97-105
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• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1926-1940
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• 1998

This paper is the part II of research results on the performance evaluation of fully interconnected ATM switch, and includes the performance evaluation results for bursty traffic and nonuniform distribution. The switch model is a fyully interconnected switch type proposed by ETRI and is the proper architecutre for a small-sized switch element. The proposed switch consists of two steps of buffering scheme in the switch fabric in order to effectively absorb the effect of bursty nature of ATM traffic. The switch uses bit addressing method for addressing shcmeme and thus it is easy to implement multicasting function without adding additional functional block. In order to incorporate the bursty nature of traffic in ATM networks, we use IBP(Interrupted Bernoulli Process) model as an input traffic model as well as random traffic model which has been used as a traditional traffic model. In order to design the various scenarios for simulation, we considered both uniform and nonuniform output distribution, and also implemented multicast function. In this paper, we presented the simulation results in diverse environments and evaluated the performance of the switch.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.247-250
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• 2006

This paper presents the single-stage High Power Factor TSFC(Two-Switch Forward Converter). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contents of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations are illustrated and verified through the experiment with a 200W(5V, 40A) 200kHz MOSFET based experimental circuit.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.161-170
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• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.169-172
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• 2006

This paper presents the single-stage High Power Factor AC/DC Two-Switch Forward Converter (TSFC). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contents of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations are illustrated and verified through the simulation with a 200W(5V, 40A) 200kHz MOSFET based experimental circuit.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1566-1577
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• 2015

A novel high step-up converter is presented herein, which combines the conventional buck-boost converter, the charge pump capacitor and the coupling inductor. By doing so, a quite high voltage conversion ratio due to not only the turns ratio but also the duty cycle, so as to increase design feasibility. It is noted that the denominator of the voltage conversion ratio is the square of one minus duty cycle. Above all, there is no voltage spike across the switch due to the leakage inductance and hence no passive or active snubber is needed, and furthermore, the used switch is driven without isolation and hence the gate driving circuit is relatively simple, thereby upgrading the industrial application capability of this converter. In this paper, the basic operating principles and the associated mathematical deductions are firstly described in detail, and finally some experimental results are provided to demonstrate the effectiveness of the proposed high step-up converter.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.157-161
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• 2000

The electronic ballasts for low pressure discharge lamps are produced and commercialized. However, the electronic ballasts for high pressure lamps are now in progress because of poor reliability and high cost. The major case of troubles with electronic ballasts are thermal destruction of semiconductor output switches due to non ideal i-v characteristics of switch. The loss converts to heat and rises the temperature of switch and it increases proportionally to switching frequency and value of current and voltage. This study shows the variable frequency ballasts which can suppress the heating of switches efficiently. It is used for the limitation the switch current and the rising temperature of switch by impedance variation of lamp inductor. As a result, initial warm-up time of the proposed ballasts was faster than that of magnetic ballasts about 90 msec. Power factor of tested ballasts follow as ; input and output average of magnetic ballasts are 93 [%] and 86 [%], respectively, And proposed ballasts are 97 [%] and 99 [%], respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.85-91
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• 2008

A Boost Power Factor Correction (PFC) Converter employing Zero Voltage Switching (ZVS) based Compound Active Clamping (CAC) technique is presented in this paper. An Electro Magnetic Interference (EMI) Filer is connected at the line side of the proposed converter to suppress Electro Magnetic Interference. The proposed converter can effectively reduce the losses caused by diode reverse recovery. Both the main switch and the auxiliary switch can achieve soft switching i.e. ZVS under certain condition. The parasitic oscillation caused by the parasitic capacitance of the boost diode is eliminated. The voltage on the main switch, the auxiliary switch and the boost diode are clamped. The principle of operation, design and simulation results are presented here. A prototype of the proposed converter is built and tested for low input voltage i.e. 15V AC supply and the experimental results are obtained. The power factor at the line side of the converter and the converter efficiency are improved using the proposed technique.