• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.06a
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• pp.513-514
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• 2007

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.4
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• pp.274-279
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• 2002

ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.

• Archives of design research
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• v.15 no.3
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• pp.93-102
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• 2002

The changing pattern of living and communication, combined with wireless technologies has given rise to more fluidity between spaces and relationships. Despite this, the way we use technology and the qualities of product and service are limited. For example, ON or OFF is like BLACK or WHITE, it presents a harsh distinction This severity in definition can make me uncomfortable when using products. The aim of this project is to improve the use of a product's functions and Qualities. As an example, the switch button has limited the possible interaction of a product. even each function is different. 1 intend this study is to imbue the switch with a greater freedom of interpretation. What will happen If I create a journey in between on and off\ulcorner For instance, time, pattern, state, rhythm and so on are analogue properties of a switch. The playful, spontaneous, and enjoyable behaviour of a switch will be able to bring other qualities of function and service. The switch will then be able to be an object with more human qualities, not simply an on and off button.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.111-114
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• 2005

The isolation performance of the S-band single-pole single-throw (SPST) monolithic microwave integrated circuit (MMIC) switch with two different RF-interconnection approaches, microstrip and grounded coplanar waveguide (GCPW) lines, are investigated. On-to-off isolation is improved by 5.8 dB with the GCPW design compared with the microstrip design and additional improvement of 6.9dB is obtained with the coplanar wire-bond interconnection (CWBI) at 3.4 GHz. The measured insertion loss and third-order inter-modulation distortion (IMD3) are less than 2.43 dB over 2.5 CHz $\sim$ 4 GHz and greater than 64 dBc.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.11-16
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• 2004

This paper proposes the overload reduction method for the connection information audit processor in ATM switch. Based on this method, we design the simple IPC exchange method and non-stop auditing method for IPC loss. We evaluate the performance about the proposed Audit method. At the result of evaluation, we figure out that the p개posed audit method reduces the load of call control processor because of a fewer IPC and prevent stopping audit function for IPC loss because of requesting the lost connection information again. Therefore, we confirm that the proposed audit method can reestablish a Mismatched connection information with a little load and elevate correctness about audit function.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.369-372
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• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1732-1735
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• 2002

A $\kappa$-side switch box with W terminals on each side is said to be hyper universal, denoted by ($\kappa$, W)-HUSB, if it is routable for any global .outing with density at most W. In [5], we have proposed a switch box design strategy and designed a near optimum (4, W)-HUSB F(W) with 6.W switches. In this paper, we design, analyze and implement an efficient detailed routing algorithm for the S-box F(W). This router. can accommodate all routing requirement topologies.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.60-63
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• 2003

This paper describes the design and the simulation of a V-band single pole double throw (SPDT) FET switch fur millimeter-wave applications using drain impedance transformation network with CPW transmission line. The designed switch has about 10% bandwidth at 60GHz. Insertion loss is better than 3dB fur the ON state and Isolation is larger than 30dB fer the OFF state. The maximum isolation is 43.4dB at 60GHz with input power of 10dBm. The yield analysis is done considering the effects of pHEMT variations.

• Journal of information and communication convergence engineering
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• v.9 no.1
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• pp.74-77
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• 2011

PSPICE modeling of a commercial LED driver IC (TOP245P) and PC817A optocoupler is proposed for the switch-mode power supply (SMPS) (applicable to LED driver) design and simulation. An analog behavioral model of the TOP245P IC including the shunt regulator, under-voltage(UV) detection, over-voltage(OV) shut-down and SR flip-flop is developed by using PSPICE. The empirical equation of PC817A current transfer ratio (CTR) is fitted from the datasheet of PC817A. Two types of SMPSs are simulated with the averaged-model and switching-model. The simulation results by the proposed PSPICE models are in good agreement with those in the data sheet and an experimental data.