• Title/Summary/Keyword: Switch Network

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A Fault Tolerant ATM Switch using a Fully Adaptive Self-routing Algorithm -- The Cyclic Banyan Network (완전 적응 자기 경로제어 알고리즘을 사용하는 고장 감내 ATM 스위치 - 사이클릭 베니안 네트웍)

  • 박재현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.9B
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    • pp.1631-1642
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    • 1999
  • In this paper, we propose a new fault tolerant ATM Switch and a new adaptive self-routing scheme used to make the switch to be fault tolerant. It can provide more multiple paths than the related previous switches between an input/output pair of a switch by adding extra links between switching elements in the same stage and extending the self-routing scheme of the Banyan network. Our routing scheme is as simple as that of the banyan network, which is based on the topological relationships among the switching elements (SE’s) that render a packet to the same destination with the regular self-routing. These topological properties of the Banyan network are discovered in this paper. We present an algebraic proof to show the correctness of this scheme, and an analytic reliability analysis to provide quantitative comparisons with other switches, which shows that the new switch is more cost effective than the Banyan network and other augmented MIN’s in terms of the reliability.

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A Study on the Virtual Switch Implementation and Comparison for Smart Node Platform (가상 스위치 구현 및 비교에 관한 연구)

  • Jeong, Gab Joong;Choi, Kang-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.12
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    • pp.2911-2918
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    • 2014
  • Nowadays, most Internet servers run on virtual a network which connects each virtual machine, to process large amounts of data on single physical computer. The virtual machines for their own purposes are interconnected to other virtual server systems with various types of operating systems. Each virtual server may share one physical computer resources and operates at a service seamlessly to each other. Sometimes even the virtual machines are implemented using a method that lease the physical IT resources without purchasing physical server. Therefore, a virtual switch is needed to improve the performance when a large number of virtual machines operate on physical server. In this study, the implementation and investigation was performed for the virtual switches, OpenvSwitch and DPDKvSwitch, in order to provide the necessary high-performance cloud services to creative business.

Performance Evaluation of Networks with Buffered Switches (버퍼를 장착한 스위치로 구성된 네트워크들의 성능분석)

  • Shin, Tae-Zi;Nam, Chang-Woo;Yang, Myung-Kook
    • Journal of KIISE:Information Networking
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    • v.34 no.3
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    • pp.203-217
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    • 2007
  • In this paper, a performance evaluation model of Networks with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch networks. The characteristic of a network with crossbar switches is determined by both the connection pattern of the switches and the limitation of data flow in a each switch. In this thesis, the evaluation models of three different networks : Multistage interconnection network, Fat-tree network, and other ordinary communication network are developed. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of networks that uses the multiple buffered crossbar switches. It is shown that both the analysis and the simulation results match closely. It is also observed that the increasing rate of Normalized Throughput is reduced and the Network Delay is getting bigger as the buffer size increased.

Reliability Evaluation of a Distribution System with wind Turbine Generators Based on the Switch-section Partitioning Method

  • Wu, Hongbin;Guo, Jinjin;Ding, Ming
    • Journal of Electrical Engineering and Technology
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    • v.11 no.3
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    • pp.575-584
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    • 2016
  • Considering the randomness and uncertainty of wind power, a reliability model of WTGs is established based on the combination of the Weibull distribution and the Markov chain. To analyze the failure mode quickly, we use the switch-section partitioning method. After defining the first-level load zone node, we can obtain the supply power sets of the first-level load zone nodes with each WTG. Based on the supply sets, we propose the dynamic division strategy of island operation. By adopting the fault analysis method with the attributes defined in the switch-section, we evaluate the reliability of the distribution network with WTGs using a sequential Monte Carlo simulation method. Finally, using the IEEE RBTS Bus6 test system, we demonstrate the efficacy of the proposed model and method by comparing different schemes to access the WTGs.

Methods of constructing optimal topology to improve performance of STP (STP의 성능 향상을 위한 최적의 토폴로지 구성방법)

  • Park Sung-Han;Jang Jong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.2
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    • pp.271-275
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    • 2006
  • In STP, network performance differs depending on topology configuration. Therefore, we need to configure right topology for the optimal efficiency of networking. This paper suggest the optimal topology configuration for efficient networking between ethernet switchs. It finds out the best topology configuration by calculation mathematical model which uses transmission time between root switch and other switchs in the same domain. And it also analysed performance difference on locations of root switch. Through the performance analysis, we could conclude that placing the root switch in the center is the most efficient.

Performance Analysis of Output Queued Batcher-Banyan Switch for ATM Network (ATM 망에 적용 가능한 출력단 버퍼형 Batcher-Banyan 스위치의 성능분석)

  • Keol-Woo Yu;Kyou Ho Lee
    • Journal of the Korea Society for Simulation
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    • v.8 no.4
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    • pp.1-8
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    • 1999
  • This paper proposes an ATM switch architecture called Output Queued Batcher-Banyan switch (OQBBS). It consists of a Sorting Module, Expanding Module, and Output Queueing Modules. The principles of channel grouping and output queueing are used to increase the maximum throughput of an ATM switch. One distinctive feature of the OQBBS is that multiple cells can be simultaneously delivered to their desired output. The switch architecture is shown to be modular and easily expandable. The performance of the OQBBS in terms of throughput, cell delays, and cell loss rate under uniform random traffic condition is evaluated by computer simulation. The throughput and the average cell delay are close to the ideal performance behavior of a fully connected output queued crossbar switch. It is also shown that the OQBBS meets the cell loss probability requirement of $10^{-6}$.

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Performance Evaluation of a Buffered Fat-tree Network (Buffered Fat-tree Nework의 성능분석)

  • Cho, Sung-Lae;Shin, Tai-Z.;Yang, Myung-K.
    • Proceedings of the KIEE Conference
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    • 2000.11d
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    • pp.775-777
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    • 2000
  • 본 논문에서는 buffer를 장착한 양 방향성 $a{\times}b$ switch들로 구성된 fat-tree network의 성능 분석 기법을 제안하고, 분석 모형의 타당성을 검증하였다. 제안한 분석 기법은 먼저 스위치 내부의 데이터 이동 패턴을 확률식으로 표현하고. 나아가서 buffer를 장착한 $a{\times}b$ switch의 buffer 크기에 따른 정상상태 throughput을 간단한 수식으로 구할 수 있도록 하였다. 이를 토대로 buffer를 장착한 $a{\times}b$ switch로 구성된 fat-tree network의 성능을 분석하고, 제안한 분석모형의 실효성 입증을 위하여 simulation을 시행한 후 결과를 비교 분석하였다.

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Motivation-Based Action Selection Mechanism with Bayesian Affordance Models for Intelligence Robot (지능로봇의 동기 기반 행동선택을 위한 베이지안 행동유발성 모델)

  • Son, Gwang-Hee;Lee, Sang-Hyoung;Huh, Il-Hong
    • Proceedings of the IEEK Conference
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    • 2009.05a
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    • pp.264-266
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    • 2009
  • A skill is defined as the special ability to do something well, especially as acquired by learning and practice. To learn a skill, a Bayesian network model for representing the skill is first learned. We will regard the Bayesian network for a skill as an affordance. We propose a soft Behavior Motivation(BM) switch as a method for ordering affordances to accomplish a task. Then, a skill is constructed as a combination of an affordance and a soft BM switch. To demonstrate the validity of our proposed method, some experiments were performed with GENIBO(Pet robot) performing a task using skills of Search-a-target-object, Approach-a-target-object, Push-up-in front of -a-target-object.

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Implementation of echo canceller for mobile communications interworking switch network (스위치네트워크와 연동에 의한 이동통신용 반향제거장치 구현)

  • 오돈성;이두수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.8
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    • pp.2033-2042
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    • 1996
  • In this papre, we describe a recently implemented echo canceller for digital cellular communication of Code Division Multiple Access(CDMA) that features time sharing of digital signal processor(DSP) over four channels in one DSP to reduce per channel costs. In the Public Land Mobile Network(PLMN), it is important to cancel the echo reflected from the Public Switched Telephone Network(PSTN) side. In case of digital mobile system, the round-trip delay of the echo is in excess of about 180 milliseconds due to frame-by-frame voice coding. It is necessary to cancel the echo in PLMN. We have developed a multi-channel echo canceller tht operates with Time Switch Module in a Mobile Switching Center(MSC). The general echo canceller needs PCM trunk interface circuits and the tone detection and disabling circuits, but the multi-channel echo canceller linked with Time Switch Module does not need them. Therefore we could develop the effective and economical echo canceller.

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Study on the Design of a ATM Switch Using a Digital Hopfield Neural Network Scheduler (디지털 홉필드 신경망 스케쥴러를 이용한 ATM 스위치 설계에 관한 연구)

  • 정석진;이영주변재영김영철
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.130-133
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    • 1998
  • A imput buffer typed ATM switch and an appropriate cell-scheduling algorithm are necessary for avoiding output blocking and internal blocking respectively. The algorithm determining a set of non-blocking data cells from the queues can greatly affect on the switch's throughput as well as the behavior of the queues. In this paper bit pattern optimization combined with the Token method in presented in order to improve the performance of ATM switch. The digital Hopfield neural cell scheduler is designed and used for the maximum numbers of cells in real-time

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