• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.6
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• pp.532-537
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• 2005

In order to develop a tunable resonator which can be easily operated by DC bias and applied for microwave tunable filters and devices using ferroelectric thin or thick films, the non conductor backed-and conductor backed- coplanar stripline resonators have been designed and analyzed. They have been designed to be operated at 25 GHz which involve coplanar stripline input and output ports. The resonators have been simulated and analyzed using Ansoft HFSS. The research has been focused on the Quality factor of the coplanar stripline resonator. The conductor Q, box Q, and radiation Q of the resonators have been analyzed and calculated according to the substrate thickness & conductor width of the resonators. From these parameters, the loss factors of the coplanar stripline resonator have been investigated. The conducting Q of the coplanar stripline resonator has no relation with the thickness of dielectric substrate and increases as the conductor width increases. The box Q has no much relation with the thickness of substrate and the conductor width, which is above 2000. The radiation loss increases as the thickness of substrate and the conductor width increase. To decrease the radiation loss of the coplanar stripline resonator, a conductor backed coplanar stripline resonator has been proposed which has the unloaded Q of 170.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.75-87
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• 2001

Three different kinds of substrate used in this study : bare Cu substrate, Ni-P/Cu substrate with a Ni-P layer thickness of $5\mu\textrm{m},$ and Au/Ni-P/Cu substrate with the Ni-P and Au layers of $0.15\mu\textrm{m}$ and $5\mu\textrm{m}$ thickness respectively. The wettability of various Sn-base solders was affected by the substrate metal finish used, i.e., nickel, gold and copper. On the Au/Ni-F/Cu substrate, Sn-base solders wet better than any of the other substrate metal finishes tested. The interfacial reaction between various substrate and Sn-base solder was investigated at $70^{\circ}C,$ $100^{\circ}C,$ $120^{\circ}C,$ $150^{\circ}C,$ $170^{\circ}C$ and $200^{\circ}C$ for reaction times ranging from 0 day to 60 day. Intermetallic phases was formed along a Sn-base solder/ various substrate interface during solid-state aging. The apparent activation energy for growth of Sn-Ag/Cu, Sn-Ag-Bi/Cu, and Sn-Bi/Cu couples were 65.4, 88.6, and 127.9 Kj/mol, respectively. After isothermal aging, the fracture surface shoved various characteristics depending on aging temperature and time, and the types of BGA pad.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.7
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• pp.537-542
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• 2012

DSSCs efficiency by thickness of $TiO_2$ photoelectrode and thickness differences between two substrates studied. DSSCs is made of the doctor blade method and photoelectrode annealing temperature elevated in a different ways. In addition, cells efficiencies of according to the different thickness between $TiO_2$ photoelectrode substrate and Pt counter electrode was measured. Efficiency of DSSCs made with $TiO_2$ photoelectrode of 18 ${\mu}m$ thickness and the gap difference between the substrate 28 ${\mu}m$ shows a highest 4.805% efficiency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.121-124
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• 1999

The (Ba,Sr)TiO$_3$[BST] thin film were fabricated on the Pt/Ti/SiO$_2$/Si substrate by RF sputtering technique. The structural properties of the BST thin films were investigated with deposition time and substrate temperature by XRD. In the case of the BST thin films which has the deposition thin of 20 min, second phases and BST (111) peaks were increased with increasing the temperature of substrate. The capacitance of the BST thin film (deposition time of 20 min.) was decreased with the substrate temperature and was 1500pF with applied voltage of 1V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.658-660
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• 2004

In this paper, we have investigated electrical characteristics about doble gate MOSFET with changed oxide layer thickness of nam Sate and side gate, main gate and Si-substrate. We have known that optimum thickness of nam gate and side gate at 4nm, gate and Si-substrate at 3nm. We have applied for side gate voltage 3V, and drain voltage 1.5V. finally, we have known that importance of oxide layer thickness between main gate and Si-substrate better than main gate and side Sate.

• Tribology and Lubricants
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• v.37 no.4
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• pp.144-150
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• 2021

The most cost-effective method of reducing abrasive wear in mechanical parts is increasing their hardness with thin hard coatings. In practice, the composite hardness of the coated substrate is more important than that of the substrate or coating. After full unloading of the load applied to an indenter, its indentation hardness evaluated based on the dent created on the test piece was almost dependent on plastic deformation of the substrate. Following the first part of this study, which proposes a new Brinell hardness test method for a coated surface, the remainder of the study is focused on practical application of the method. Indentation analyses of a rigid sphere and elastic-perfect plastic materials were performed using finite element analysis software. The maximum principal stress and plastic strain distributions as well as the dent shapes according to the substrate yield stress and coating thickness were compared. The substrate yield stress had a significant effect on the dent size, which in turn determines the Brinell hardness. In particular, plastic deformation of the substrate produced dents regardless of the state of the coating layer. The hardness increase by coating behaved differently depending on the substrate yield stress, coating thickness, and indentation load. These results are expected to be useful when evaluating the composite hardness values of various coated friction surfaces.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.11
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• pp.33-41
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• 2007

Effect of finite substrate plane on the radiation characteristics of microstrip patch antennas is investigated. The variation of the characteristics of the radiation pattern due to the change of the length of a substrate is much larger than that due to the change of the width of a substrate. As the thickness of a substrate increases, the characteristics of the radiation pattern reveal more sensitive for the change of the size of a substrate.

• Journal of the Optical Society of Korea
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• v.17 no.3
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• pp.269-274
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• 2013

The effect of diffusing substrate and pillow lenses on the outcoupling efficiency of organic light-emitting diodes (OLEDs) was studied by optical simulation based on the point-dipole model. The diffusing substrate included Mie scatterers by which the condition of total internal reflection could be broken. The finite-difference time-domain method was used to obtain the intensity distribution on the transparent electrode of an OLED, which was used as a light source to carry out a ray-tracing simulation of the OLED and the diffusing substrate. It was found that the outcoupling efficiency of the OLED was sensitive to the thickness of organic layers and could be increased by 21.0% by adopting a diffusing substrate in which Mie scatterers whose radius was $2.0{\mu}m$ were included at the density of $10^7mm^{-3}$ and by 65.5% by forming one pillow lens with the radius of 2 mm on the front surface of the glass substrate. This study revealed that the outcoupling efficiency could be improved by adopting diffusing substrate and pillow lenses along with the optimization of the thickness of each layer in the OLED.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.253-256
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• 2014

$Pb(Zr_{0.52}Ti_{0.48})O_3$ thin films of $1.5{\mu}m$ thickness were grown on $Pt/Ti/Gd_3Ga_5O_{12}$ substrate by RF magnetron sputtering at annealing temperatures ranging from $550^{\circ}C$ to $700^{\circ}C$. We evaluated the residual stress, by using a William-Hall plot, as a function of the annealing temperatures of PZT thin film with a constant thickness. As a result, the residual stresses of PZT thin film of $1.5{\mu}m$ thickness were changed by varying the annealing temperature. Also, we measured the hysteresis characteristic of PZT thin films of $1.5{\mu}m$ thickness to evaluate for application of an optoelectronic device.