• Title/Summary/Keyword: Sub-50nm

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Characterisitics of RF/DC Sputter Grown-ITO/Ag/ITO Thin Films for Transparent Conducting Electrode (RF/DC 스퍼티 성장한 ITO/Ag/ITO 투명전극 박막의 특성 연구)

  • Lee, Youngjae;Kim, Jeha
    • Current Photovoltaic Research
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    • v.10 no.1
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    • pp.28-32
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    • 2022
  • We investigated the optical and electrical characteristics of ITO/Ag/ITO (IAI) 3-layer thin films prepared by using RF/DC sputtering. To measure the thickness of all thin film samples, we used scanning electron microscopy. As a function of Ag thickness we characterized the optical transmittance and sheet resistance of the IAI samples by using UV-Visible spectroscopy and Hall measurement system, respectively. While the thickness of both ITO thin films in the 3-layered IAI samples were fixed at 50 nm, we varied Ag layer thickness in the range of 0 nm to 11 nm. The optical transmittance and sheet resistance of the 3-layered IAI thin films were found to vary strongly with the thickness of Ag film in the ITO (50 nm)/Ag(t0)/ITO (50 nm) thin film. For the best transparent conducting oxide (TCO) electrode, we obtained a 3-layered ITO (50 nm)/Ag (t0 = 8.5 nm)/ITO (50 nm) that showed an avrage optical transmittance, AVT = 90.12% in the visible light region of 380 nm to 780 nm and the sheet resistance, R = 7.24 Ω/□.

IR Absorption Property in NaNo-thick Nickel Cobalt Composite Silicides (나노급 두께의 Ni50Co50 복합 실리사이드의 적외선 흡수 특성 연구)

  • Song, Oh Sung;Kim, Jong Ryul;Choi, Young Youn
    • Korean Journal of Metals and Materials
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    • v.46 no.2
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    • pp.88-96
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    • 2008
  • Thermal evaporated 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films were deposited to examine the energy saving properties of silicides formed by rapid thermal annealing at temperature ranging from 500 to $1,100^{\circ}C$ for 40 seconds. Thermal evaporated 10 nm-Ni/(70 nm-poly)Si films were also deposited as a reference using the same method for depositing the 10 nm-$Ni_{50}Co_{50}$/(70 nm-poly)Si films. A four-point probe was used to examine the sheet resistance. Transmission electron microscopy (TEM) and X-ray diffraction XRD were used to determine cross sectional microstructure and phase changes, respectively. UV-VIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were used to examine the near-infrared (NIR) and middle-infrared (MIR) absorbance. TEM analysis confirmed that the uniform nickel-cobalt composite silicide layers approximately 21 to 55 nm in thickness had formed on the single and polycrystalline silicon substrates as well as on the 25 to 100 nm thick nickel silicide layers. In particular, nickel-cobalt composite silicides showed a low sheet resistance, even after rapid annealing at $1,100^{\circ}C$. Nickel-cobalt composite silicide and nickel silicide films on the single silicon substrates showed similar absorbance in the near-IR region, while those on the polycrystalline silicon substrates showed excellent absorbance until the 1,750 nm region. Silicides on polycrystalline substrates showed high absorbance in the middle IR region. Nickel-cobalt composite silicides on the poly-Si substrates annealed at $1,000^{\circ}C$ superior IR absorption on both NIR and MIR region. These results suggest that the newly proposed $Ni_{50}Co_{50}$ composite silicides may be suitable for applications of IR absorption coatings.

Ultra Shallow Junction wish Source/Drain Fabricated by Excimer Laser Annealing and realized sub-50nm n-MOSFET (엑시머 레이져를 이용한 극히 얕은 접합과 소스, 드레인의 형성과 50nm 이하의 극미세 n-MOSFET의 제작)

  • 정은식;배지철;이용재
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.562-565
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    • 2001
  • In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

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Preparation of β-TCP/TiO2 Composite by Hot-Pressing (가압소결에 의한 β-TCP/TiO2복합체의 제조)

  • 정항철;이종국
    • Journal of the Korean Ceramic Society
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    • v.41 no.3
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    • pp.202-209
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    • 2004
  • Hydroxyapatite(HA)/TiO$_2$ composite powders were prepared by mixing of spherical TiO$_2$ (10-15 nm, 500 nm) and needle-shaped HA (50-70 nm, 120-250 nm) powders which had been synthesized through precipitation, sol-gel and hydrothermal methods. From the three types of starting composite powders (HA/TiO$_2$ wt% of 75/25, 50/50, and 25/75), dense $\beta$-TCP/TiO$_2$ composites were prepared by hot-pressing at 800-100$0^{\circ}C$ for 30 min under the pressure of 30 ㎫ in Af atmosphere. The $\beta$-TCP/TiO$_2$ composites showed different microstructures and sintering densities depending on their powder morphology, composition and sintering temperature. With increasing the sintering temperature and the content of TiO$_2$, sintered density was increased and microstructure became more homogeneous.

Characteristics analysis of Sub-50nm Double Gate MOSFET (Sub-50nm Double Gate MOSFET의 특성 분석)

  • 김근호;고석웅;이종인;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.486-489
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    • 2002
  • In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

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Electrical and Optical Properties of ITO Thin Films with Various Thicknesses of SiO2 Buffer Layer for Capacitive Touch Screen Panel (정전용량식 터치스크린 패널을 위한 SiO2 버퍼층 두께에 따른 ITO 박막의 전기적 및 광학적 특성)

  • Yeun-Gun, Chung;Yang-Hee, Joung;Seong-Jun, Kang
    • The Journal of the Korea institute of electronic communication sciences
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    • v.17 no.6
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    • pp.1069-1074
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    • 2022
  • In this study, we prepared ITO thin films on the Nb2O5/SiO2 double buffer layer and investigated electrical and optical properties according to the change of SiO2 buffer layer thickness (40~50nm). The ITO thin film fabricated on the Nb2O5/SiO2 double buffer layer exhibited a broad surface roughness with a small value ranging of 0.815 to 1.181nm, and the sheet resistance was 99.3 to 134.0Ω/sq. It seems that there is no problem in applying the ITO thin film to a capacitive touch screen panel. In particular, the average transmittance in the short-wavelength (400~500nm) region and the chromaticity (b*) of the ITO thin film deposited on the Nb2O5(10nm)/SiO2(40nm) double buffer layer showed significantly improved results as 83.58% and 0.05, respectively, compared to 74.46% and 4.28 of ITO thin film without double buffer layer. As a result, it was confirmed that optical properties such as transmittance in the short-wavelength region and chromaticity were remarkably improved due to the index matching effect in the ITO thin film with the Nb2O5/SiO2 double buffer layer.

Fabrication and Densification of a Nanocrystalline CoSi Compound by Mechanical Alloying and Spark Plasma Sintering

  • Chung-Hyo Lee
    • Korean Journal of Materials Research
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    • v.33 no.3
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    • pp.101-105
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    • 2023
  • A mixture of elemental Co50Si50 powders was subjected to mechanical alloying (MA) at room temperature to prepare a CoSi thermoelectric compound. Consolidation of the Co50Si50 mechanically alloyed powders was performed in a spark plasma sintering (SPS) machine using graphite dies up to 800 ℃ and 1,000 ℃ under 50 MPa. We have revealed that a nanocrystalline CoSi thermoelectric compound can be produced from a mixture of elemental Co50Si50 powders by mechanical alloying after 20 hours. The average grain size estimated from a Hall plot of the CoSi intermetallic compound prepared after 40 hours of MA was 65 nm. The degree of shrinkage of the consolidated samples during SPS became significant at about 450 ℃. All of the compact bodies had a high relative density of more than 94 % with a metallic glare on the surface. X-ray diffraction data showed that the SPS compact produced by sintering mechanically alloyed powders for 40-hours up to 800 ℃ consisted of only nanocrystalline CoSi with a grain size of 110 nm.

Application of Generalized Scaling Theory for Nano Structure MOSFET (나노 구조 MOSFET에서의 일반화된 스케일링의 응용)

  • 김재홍;김근호;정학기;이종인
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.275-278
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    • 2002
  • As the gate lengths of MOSFETs are scaled down to sub-50nm regime, there are key issues to be considered in the device design. In this paper, we have investigated the characteristics of threshold voltage for MOSFET device. We have simulated the MOSFETs with gate lengths from 100nm to 30nm using generalized scaling. Then, we have known the device scaling limits for nano structure MOSFET. We have determined the threshold voltages using LE(Linear Extraction) method.

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Thickness Optimization of SiO2/Al2O3 Stacked Layer for High Performance pH Sensor Based on Electrolyte-insulator-semiconductor Structure (SiO2/Al2O3 적층 감지막의 두께 최적화를 통한 고성능 Electrolyte-insulator-semiconductor pH 센서의 제작)

  • Gu, Ja-Gyeong;Jang, Hyun-June;Cho, Won-Ju
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.1
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    • pp.33-36
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    • 2012
  • In this study, the thickness effects of $Al_2O_3$ layer on the sensing properties of $SiO_2/Al_2O_3$ (OA) stacked membrane were investigated using electrolyte-insulator-semiconductor (EIS) structure for high quality pH sensor. The $Al_2O_3$ layers with a respective thickness of 5 nm, 15 nm, 23 nm, 50 nm, and 100 nm were deposited on the 5-nm-thick $SiO_2$ layers. The electrical characteristics and sensing properties of each OA membranes were investigated using metal-insulator-semiconductor (MIS) and EIS devices, respectively. As a result, the OA stacked membrane with 23-nm-thick $Al_2O_3$ layer shows the excellent characteristics as a sensing membrane of EIS sensor, which can enhance the signal to noise ratio.

Three-key Triple Data Encryption Algorithm of a Cryptosystem Based on Phase-shifting Interferometry

  • Seok Hee Jeon;Sang Keun Gil
    • Current Optics and Photonics
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    • v.7 no.6
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    • pp.673-682
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    • 2023
  • In this paper, a three-key triple data encryption algorithm (TDEA) of a digital cryptosystem based on phase-shifting interferometry is proposed. The encryption for plaintext and the decryption for the ciphertext of a complex digital hologram are performed by three independent keys called a wavelength key k1(λ), a reference distance key k2(dr) and a holographic encryption key k3(x, y), which are represented in the reference beam path of phase-shifting interferometry. The results of numerical simulations show that the minimum wavelength spacing between the neighboring independent wavelength keys is about δλ = 0.007 nm, and the minimum distance between the neighboring reference distance keys is about δdr = 50 nm. For the proposed three-key TDEA, choosing the deviation of the key k1(λ) as δλ = 0.4 nm and the deviation of the key k2(dr) as δdr = 500 nm allows the number of independent keys k1(λ) and k2(dr) to be calculated as N(k1) = 80 for a range of 1,530-1,562 nm and N(dr) = 20,000 for a range of 35-45 mm, respectively. The proposed method provides the feasibility of independent keys with many degrees of freedom, and then these flexible independent keys can provide the cryptosystem with very high security.