• Title/Summary/Keyword: Storage Buffer

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Proteome Approach as a Tool for the Efficient Separation of Seed Storage Proteins from Buckwheat

  • Cho, Seong-Woo;Kwon, Soo-Jeong;Roy, Swapan Kumar;Woo, Sun-Hee
    • KOREAN JOURNAL OF CROP SCIENCE
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    • v.60 no.1
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    • pp.29-32
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    • 2015
  • Two-dimensional electrophoresis (2-DE) was executed to separate the seed storage proteins from the buckwheat. The proteins extracted from the whole seed proteins were better separated and observed in the use of lysis buffer. Using this method, the highly reproducible isoelectric focusing (IEF) can be obtained from polyacrylamide gels, and IEF from the polyacrylamide gel at all the possible pH range (5.0-8.0) was more easily separated than IPG (immobilized pH gradient) gels. The polyacrylamide gels in the first dimension in 2-DE was used to separate and identify a number of whole seed proteins in the proteome analysis. In this new apparatus using 2-DE, 27cm in length of plate coated with polyacrylamide gel was used and the experiment was further investigated under the various conditions.

Effect of cholesterol into liposome on the stabilization of incorporated retinol

  • Lee, Jae-Uk;Lee, Soo-Jin;Kang, Joo-Sung;Lee, Kyung-Eun;Kim, Jin-Ju;Lee, Seung-Cheol
    • Proceedings of the SCSK Conference
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    • 2003.09b
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    • pp.60-72
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    • 2003
  • To investigate the effect of cholesterol in liposome on the stability of incorporated retinol, the physico-chemical experiments for various amounts of cholesterol-containing liposomes were performed. Liposome with retinol containing cholesterol was prepared as multilamella vesicles(MLVs) by dehydration/rehydration method. The incorporation efficiency of retinol into liposome was maximized as 99.31 % at 50:50 (phosphatidylcholine/cholesterol) at pH 9. The stability of incorporated retinol at low storage temperature was enhanced with increasing cholesterol content than at high storage temperature. For example, incorporated retinol in liposome at glycine buffer(pH 9} was degraded slowly during storage at 4. The degradation of retinol in liposomes was slower at pH 9 than at pH 7. These results supported that cholesterol in liposome increased largely the stability of incorporated retinol.

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SWSC(Sequential Write Spatial Clock) Buffer Replacement Algorithm For Mobile Flash Storage (모바일 플래시 저장장치를 위한 SWSC(Sequential Write Spatial Clock) 버퍼 교체 알고리즘)

  • Lee, Mikyung;Lee, Duki;Shin, Mincheol;Park, Sanghyun
    • Proceedings of the Korea Information Processing Society Conference
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    • 2014.11a
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    • pp.771-774
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    • 2014
  • 지난 몇 년간 스마트폰은 굉장히 빠른 속도로 발전하면서 생활 속에서 큰 비중을 차지하고 있다. 이러한 스마트폰에는 에너지 효율, 크기, 속도 면에서 모바일 기기에 적합한 Flash storage가 탑재되고 있다. 이 논문에서는 스마트폰에 탑재된 Flash storage를 기반으로 한 버퍼 교체 알고리즘들 가운데 Spatial Clock 알고리즘에 초점을 맞추고 있다. 그리고 이 알고리즘이 Video Streaming workload에서 성능 발휘를 하지 못한다는 점을 해결하기 위해 SWSC(Sequential Write Spatial Clock) 알고리즘을 제안하였다. 이 알고리즘은 dirty 페이지들이 연속적인 경우 sequential write를 수행한다. 따라서 write 수행시간을 줄일 수 있고 결과적으로 Video Streaming workload에서도 좋은 성능을 발휘할 수 있다.

Planning for Safely Control on Hazardous Material Distribution Depot.

  • Roh, S.K.;Jun, S.W.;Kang, T.H.;Seo, Y.M.
    • Proceedings of the Korea Institute of Fire Science and Engineering Conference
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    • 1997.11a
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    • pp.260-268
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    • 1997
  • The safety of LPG vessel storage has been simply designed and controled with blast wave barrier structure concept regardless of its quantity or hazardous situation. The limit of regal controls on LPG vessel storage need to be identified in terms of safety buffer distance from LPG explosion. The level of overpressure effect and heat radiation In the safety structure and neighbouring human activity required to be estimated to find the gap between existing controls on such storage. To this content the paper discuss the issues on the approach In the blast wave barrier and safety separation distances.

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FAST : A Log Buffer Scheme with Fully Associative Sector Translation for Efficient FTL in Flash Memory (FAST :플래시 메모리 FTL을 위한 완전연관섹터변환에 기반한 로그 버퍼 기법)

  • Park Dong-Joo;Choi Won-Kyung;Lee Sang-Won
    • The KIPS Transactions:PartA
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    • v.12A no.3 s.93
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    • pp.205-214
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    • 2005
  • Flash memory is at high speed used as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make an overwrite possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem the flash memory controller maintains a system software module called the flash translation layer(FTL). Of many proposed FTL schemes, the log block buffer scheme is best known so far. This scheme uses a small number of log blocks of flash memory as a write buffer, which reduces the number of erase operations by overwrites, leading to good performance. However, this scheme shows a weakness of low page usability of log blocks. In this paper, we propose an enhanced log block buffer scheme, FAST(Full Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the log block buffer scheme.

Design and Implementation of File System Using Local Buffer Cache for Digital Convergence Devices (디지털 컨버전스 기기를 위한 지역 버퍼 캐쉬 파일 시스템 설계 및 구현)

  • Jeong, Geun-Jae;Cho, Moon-Haeng;Lee, Cheol-Hoon
    • The Journal of the Korea Contents Association
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    • v.7 no.8
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    • pp.21-30
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    • 2007
  • Due to the growth of embedded systems and the development of semi-conductor and storage devices, digital convergence devises is ever growing. Digital convergence devices are equipments into which various functions such as communication, playing movies and wave files and electronic dictionarys are integrated. Example are portable multimedia players(PMPs), personal digital assistants(PDAs), and smart phones. Therefore, these devices need an efficient file system which manages and controls various types of files. In designing such file systems, the size constraint for small embedded systems as well as performance and compatibility should be taken into account. In this paper, we suggest the partial buffer cache technique. Contrary to the traditional buffer cache, the partial buffer cache is used for only the FAT meta data and write-only data. Simulation results show that we could enhance the write performance more than 30% when the file size is larger than about 100 KBytes.

Design Optimization Techniques for the SSD Controller (SSD 컨트롤러 최적 설계 기법)

  • Yi, Doo-Jin;Han, Tae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.8
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    • pp.45-52
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    • 2011
  • Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

Hybrid Main Memory based Buffer Cache Scheme by Using Characteristics of Mobile Applications (모바일 애플리케이션의 특성을 이용한 하이브리드 메모리 기반 버퍼 캐시 정책)

  • Oh, Chansoo;Kang, Dong Hyun;Lee, Minho;Eom, Young Ik
    • Journal of KIISE
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    • v.42 no.11
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    • pp.1314-1321
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    • 2015
  • Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

CPWL : Clock and Page Weight based Disk Buffer Management Policy for Flash Memory Systems

  • Kang, Byung Kook;Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.2
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    • pp.21-29
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    • 2020
  • The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.

Dynamic Buffer Partitioning Technique for Efficient Continuous Media Service in VOD Servers (VOD 서버에서 효율적인 연속미디어 서비스를 위한 동적 버퍼 분할 기법)

  • Kwon, Chun-Ja;Choi, Chang-Yeol;Choi, Hwang-Kyu
    • The KIPS Transactions:PartA
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    • v.9A no.2
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    • pp.137-146
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    • 2002
  • In VOD server, in order to guarantee playback of continuous media, such as video, without hiccups for multiusers, the server has to manage its buffer sophisticatedly by prefeching a part of the data into the buffer As the continuous media data buffered by one user can be used again by the others, the number of disk accesses is reduced and then the latency time far the users is also reduced. In this paper, we propose a new buffer management technique for continuous media in VOD server. Our basic algorithm partitions the buffer into groups and then a group of buffer which has the lowest utilization is chosen and partitioned again for a new user. The basic algorithm is extended for supporting multiple streams and clip data and for providing VCR functions. Our proposed technique is able to increase in the number of concurrent users as increasing the utilization of the buffer and to minimize the average waiting time for multiuser accesses as the bandwidth of storage is slowly reached to the limit. In the simulation study for comparing the performance of our technique with that of the existing techniques, we show that the average waiting time is reduced mere than 50% and the number of concurrent users increases by 1 ∼5% as compared with those of the exiting techniques.