• 전기학회논문지
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• 제58권2호
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• pp.232-238
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• 2009

Flicker, also known as voltage fluctuation, is a newest problem of power quality issues, because it is caused by nonlinear loads such as electrical arc furnace and large-scale induction motor, which are country-widely used as the heavy industries of a country develop. An international standard, International Electrotechnical Commission (IEC) 61000-4-15, was published in 1997 and revised in 2003. With increasing concerns about flicker, its mitigation methods have been also studied. General countermeasures for flicker are divided into three categories: a) enhancing the capacity of supplying system, b) Series elements including series reactor and series capacitor and c) power electronic devices including static VAR compensator (SVC) and static synchronous compensator (STATCOM). This paper introduces how to mitigate the voltage flicker at the point of common coupling (PCC) and presents how to simulate and compare the flicker alleviating effects by each mitigation method, using IEC flickermeter based on the Matlab/Simulink program.

• 전기학회논문지
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• 제57권12호
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• pp.2255-2262
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• 2008

This paper presents a design parameter calculation methodology and its realization to construction for the damped oscillatory impulse current generator(ICG) modelled as damping factor $\alpha$. Matlab internal functions, "fzero" and "polyfit" are applied to find a which are solutions of second order nonlinear equation related with three wave parameters $T_{1},T_{2}$ and $I_{os}$. The calculation results for standard impulse current waveforms such as 4/10${\mu}s$, 8/20${\mu}s$ and 30/80${\mu}s$ show very good accuracy and this results make it possible to extend to generalization in the design of damped oscillatory lCG with any capacitor. 8/20${\mu}s$ ICG based on the calculated design circuit parameters is fabricated in consideration of the nonlinear load(MOV) variation. Comparisons of the tested waveforms with the designed estimation show error within 10% for the waveform tolerance recommended in IEC 60060-1 and IEEE std. C62.45.

• 한국공작기계학회논문집
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• 제17권2호
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• pp.110-113
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• 2008

Embedded capacitor technology is one of the effective packing technologies for further miniaturization and higher performance of electric packaging system. In this paper, the embedded capacitors were simulated and fabricated in 8-layered printed circuit board employing standard PCB processes. The composites of barium titanante($BaTiO_3$) powder and epoxy resin were employed for the dielectric materials in embedded capacitors. Theoretical considerations regarding the embedded capacitors have been paid to understand the frequency dependent impedance behavior. Frequency dependent impedance of simulated and fabricated embedded capacitors was investigated. Fabricated embedded capacitors have lower self resonance frequency values than that of the simulated embedded capacitors due to the increased parasitic inductance values. Frequency dependent capacitances of fabricated embedded capacitors were well matched with those of simulated embedded capacitors from the 100MHz to 10GHz range. Quality factor of 20 was observed and simulated at 2GHz range in the 10 pF embedded capacitors. Temperature dependent capacitance of fabricated embedded capacitors was presented.

• 대한전기학회논문지:전력기술부문A
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• 제48권4호
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• 한국재료학회지
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• 제31권2호
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• pp.84-91
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• 2021

To cope with automobile exhaust gas regulations, ISG and charging control systems are applied to HEV vehicles for the purpose of improving fuel economy. These systems require quick charge-discharge performance of high current. Therefore, a Module of the AGM battery with high energy density and EDLC(Electric Double Layer Capacitor) with high power density are constructed to study the charging and discharging behavior. In CCA, which evaluates the starting performance at -18 ℃ & 30 ℃ with high current, EDLC contributed for about 8 sec at the beginning. At 0 ℃ CA (Charge Acceptance), the initial Charging current of the AGM/EDLC Module, is twice that of the AGM lead acid battery. To play the role of EDLC during high-current rapid charging and discharging, the condition of the AGM lead-acid battery is optimally maintained. As a result of a Standard of Battery Association of Japan (SBA) S0101 test, the service life of the Module of the AGM Lead Acid Battery/EDLC is found to improve by 2 times compared to that of the AGM Lead Acid Battery.

• 한국안전학회지
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• 제35권1호
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• pp.1-11
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• 2020

Article 325 (Prevention of Fire Explosion due to Electrostatic) of the Rule for Occupational Safety and Health Standard specifies that in order to prevent the risk of disasters caused by static electricity, fire, explosion and static electricity in the production process, However, in order to do this, it is absolutely necessary to use a pre-detection technology and a detector for antistatic discharge prediction, which is a precautionary measure by static electricity in a fire / explosion hazard place, but in Korea, And there is no technical standard for the application of the technology of the explosion proof structure of the related equipment. Research methods include domestic and overseas electrostatic discharge detection technology and literature investigation of related equipment explosion proofing technology, domestic and foreign electrostatic discharge detection device production and use situation investigation, advanced foreign technology data analysis and benchmarking. In particular, we sought to verify the results of empirical experiments using electrostatic discharge detection technology through sample purchase and analysis of related major products, development of optimization technology through prototype production, evaluation, and supplementation, and expert knowledge through expert consultation. The results of this study were developed and fabricated two prototypes of electrostatic discharge detector based on the technology / standard related to electrostatic discharge detection technology in Korea and abroad through development of electrostatic discharge detection technology and development and production of detector. In addition, based on the development of electrostatic discharge detection technology, we developed an intrinsic safety explosion proof ib class explosion proof technology applicable to the process of using and handling flammable gas and flammable liquid vapor and combustible dust. In the case of the over voltage and minimum voltage are supplied to the explosion-proof structure ESD detector, check the state of the circuit and the transient and transient currents generated by the coil and capacitor elements during the input and standby of the signal pulse voltage. Explosion-proof equipment-Part 11: Intrinsically safe explosion proof structure The comparative evaluation with the reference curve in Annex A of "i" confirms that the characteristics of the intrinsically safe explosion protection structure are met.

• Journal of Power Electronics
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• 제15권3호
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• pp.621-633
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• 2015

This paper proposes the analysis and design of a DC-side symmetrical zero-current-switching (ZCS) Class-D current-source driven resonant rectifier to improve the low power-factor and high line current harmonic distortion of lighting applications. An analysis of the junction capacitance effect of Class-D ZCS rectifier diodes, which has a significant impact on line current harmonic distortion, is discussed in this paper. The design procedure is based on the principle of the symmetrical Class-D ZCS rectifier, which ensures more accurate results and provides a more systematic and feasible analysis methodology. Improvement in the power quality is achieved by using the output characteristics of the DC-side Class-D ZCS rectifier, which is inserted between the front-end bridge-rectifier and the bulk-filter capacitor. By using this symmetrical topology, the conduction angle of the bridge-rectifier diode current is increased and the low line harmonic distortion and power-factor near unity were naturally achieved. The peak and ripple values of the line current are also reduced, which allows for a reduced filter-inductor volume of the electromagnetic interference (EMI) filter. In addition, low-cost standard-recovery diodes can be employed as a bridge-rectifier. The validity of the theoretical analysis is confirmed by simulation and experimental results.

• 한국산학기술학회논문지
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• 제14권7호
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• pp.3425-3430
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• 2013

최근 이동통신 시장의 급속한 증가에 따라 단말기 설계는 다표준 방식으로 발전하고 있다. 본 논문에서는 다표준 이동통신 시스템에 적용할 수 있는 주파수 가변형 능동 RC 대역통과 필터를 능동 인덕터를 사용하여 설계하였다. 기존의 대역통과 필터 설계법에서는 저지대역의 감쇠 특성과 통과대역의 주파수 선택도를 향상시키기 위하여 필터의 차수를 높게 하거나 극점 Q를 증가시키는 설계법을 사용한다. 본 논문에서는 극점 Q가 높은 능동 인덕터로 대역통과 필터를 설계하여 주파수 특성이 향상되었다. 또한 설계된 대역통과 필터는 튜닝 회로를 이용하여 필터의 중심주파수와 이득을 간단히 조절할 수 있도록 제안하였다. 설계된 능동 RC 대역통과 필터 특성은 TSMC $0.18{\mu}m$ 공정 파라미터를 이용하여 해석하였다. 시뮬레이션 결과, Q=20.5를 갖는 능동 인덕터를 이용한 필터는 1.86GHz 중심주파수에서 90MHz의 대역폭을 갖고, 튜닝 회로의 커패시터 값으로 중심주파수를 1.86~2.38GHz 범위까지 튜닝이 가능하여 다표준 무선통신 시스템에 적용할 수 있다.

• 전기전자학회논문지
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• 제15권1호
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• pp.57-63
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• 2011

본 논문에서는 대역폭 조정이 가능한 다중 생체 신호 처리용 대역 통과 필터 회로에 관한 것이다. 일반적인 대역 통과 필터는 출력 단에 연결되는 커패시터 배열의 값을 조절하여 고역 -3dB 차단 주파수를 결정한다. 하지만 본 논문에서 제안하는 대역 통과 필터 회로는 커패시터 대신에, 증폭기에 사용되는 바이어스 전압을 통해 증폭기의 트랜스 컨덕턴스 값을 조절하여 차단 주파수를 조절한다. 이러한 방법은 기존의 방식보다 칩 면적을 최소한 1/10로 줄일 수 있어 저면적 설계가 가능하다. 조정 가능한 고역 -3dB 차단 주파수의 대역은 100Hz에서 1KHz이며 사용된 공정은 0.18um CMOS 표준 공정이다. 저 전력 설계를 위해 회로는 서브 스레쉬 홀드 영역에서 동작하며 공급전압은 1V이고, 회로의 총 전류 소모는 1uA이다.

• 한국산학기술학회논문지
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• 제7권4호
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• pp.616-624
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• 2006

본 논문은 집중소자가 결합된 결함접지구조를 갖는 초고주파 전송선로의 전기적 특성에 관하여 기술하고 있다. 주기구조의 일종인 결함접지구조를 전송선로에 삽입하면, 등가의 부가적인 인덕턴스와 캐패시턴스에 의하여 표준형 전송선로에는 없던 저역통과, 대역차단 또는 대역통과 특성이 발생하며, 전송선로의 전기적 길이가 늘어나는 지연파 특성이 나타난다. 여기에 다시 저항, 캐패시터, 인덕터와 같은 집중소자가 결합되면 공진주파수의 변화를 포함한 다양한 전송특성의 변화가 발생한다. 본 논문에는 결합되는 집중소자들의 값에 따른 DGS 전송선로의 특성 변화를 예측하고 실험적으로 검증하였다.