• 전자공학회논문지C
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• 제35C권7호
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• pp.1-10
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• 1998

The first thing in designing application-specific instruction set processor is having instruction set closely matching hardware characteristics. This instruction set design problem can be more complicated when cobined with implementation method selection problem of each instruction. Our processor model supports two kinds of instructions-primitive or special instructions. Primitive instructions are implemented using common multifunctional hardware such as ALU. Special instructions require a set of dedicated hardware, which actually functions as a coprocessor to the main processor. In this case, special instructions and primitive instructions can be executed independently. In this paper, we present novel algorithm for genrating special instructions for given application. Parallelism between special instructions and primitive instructions is also considered during the performance estimation stage of generated special instructions.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.333-336
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• 2002

In many cases, fuzzy modeling has a defect that the design procedure cannot be theoretically justified. To overcome this difficulty, we suggest a new design method for fuzzy model by combining genetic algorithm(GA) and mush set theory. GA, which has the advantages is optimization, and rule base. However, it is some what time consuming, so are introduce rough set theory to the rule reduction procedure. As a result, the decrease of learning time and the considerable rate of rule reduction is achieved without loss of useful information. The preposed algorithm is composed of three stages; First stage is quasi-optimization of fuzzy model using GA(coarse tuning). Next the obtained rule base is reduced by rough set concept(rule reduction). Finally we perform re-optimization of the membership functions by GA(fine tuning). To check the effectiveness of the suggested algorithm, examples for time series prediction are examined.

• 한국측량학회지
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• 제13권1호
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• pp.1-12
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• 1995

본 연구에서는 국립지리원에서 20여년간(1975-1994) 관측한 정밀 1차 측지망 자료를 연도(작업구역)별, 블록별로 조정하여 전산처리에 필요한 데이타 Set로 구축하고, 전국 동시망 조정을 실시하여 우리 나라 측지망의 정확도 평가 및 오차전파 상태, 국토의 수평지각변동을 파악하였다. 이를 토대로 우리 나라 최초의 동질성 있는 정밀 1차 기준점(1, 2등 삼각점)의 실용성과 (기준점 좌표 94)를 산정 제시하였다.

• Journal of the Korean Association of Oral and Maxillofacial Surgeons
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• 제35권5호
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• pp.316-323
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• 2009

Purpose: This study was performed to evaluate three-dimensional positional change of the condyle using 3D CT after bilateral sagittal split ramus osteotomy (BSSRO) in skeletal class III patients. Patients and methods: Nine patients who underwent BSSRO for mandibular set-back in skeletal class III malocclusion without facial asymmetry were examined. Miniplates were used for the fixation after BSSRO. 3-D CT was taken before, immediately after, and 6 months after undergoing BSSRO. After creating 3D-CT images using V-works $4.0^{TM}$ program, axial plane, coronal plane, & sagittal plane were configured. Three dimensional positional change, from each plane to the condyle, of the nine patients was measured before, immediately after, and 6 months after undergoing BSSRO. Results: 1. The mean value of mandibular set-back for nine mandibular prognathism patients was 7.36 mm (${\pm}\;2.42\;mm$). 2. In the axial view, condyle is rotated inward immediately after BSSRO (p < 0.05), comparing with preoperative but outward 6 months after BSSRO comparing with postoperative (p < 0.05). 3. In the axial view, condyle is moved laterally immediately after BSSRO (p < 0.05), comparing with preoperative but regressed 6 months after BSSRO comparing with preoperative (p > 0.05). 4. In the frontal & coronal view, there is changed immediately after and 6 months after BSSRO, comparing with preoperative but no statistical difference. Conclusion: These results indicate that three-dimensional positional change of the condyle in skeletal class III patients is observed lateral displacement & inward rotation immediate after BSSRO, but the condyle in 6 months after BSSRO tends to regress to preoperative position.

• Journal of Electrical Engineering and Technology
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• 제5권3호
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• pp.468-476
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• 2010

This paper presents a direct single-stage power converter using single-phase isolated full-bridge converter modules, with inherent power factor correction (PFC) for a 12 kW switched mode power supply (SMPS). The advantages of the proposed converter are its simple control strategy, reduction in number of conversion stage, low input line current harmonics, and improvement in power factor. Analysis of the single-stage converter is carried out in continuous conduction mode of operation. Steady-state analysis of the proposed converter is conducted to obtain converter parameters. A systematic design procedure is also presented for a 12k W converter with a design example. The effect of load variation on SMPS is also studied in order to demonstrate the effectiveness of the proposed converter for the complete range of load conditions. A set of power quality indices on input ac mains for an SMPS fed from a single-stage converter is also presented for easy comparison of their performance.

• Journal of Communications and Networks
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• 제5권1호
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• pp.33-42
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• 2003

In this paper a two-stage maximum-likelihood (ML) detection structure for group detection in DS/CDMA systems is presented. The first stage of the receiver is a linear filter, aimed at suppressing the effect of the unwanted (i.e., out-of-grout) users' signals, while the second stage is a non-linear block, implementing a ML detection rule on the set of desired users signals. As to the linear stage, we consider both the decorrelating and the minimum mean square error approaches. Interestingly, the proposed detection structure turns out to be a generalization of Varanasi's group detector, to which it reduces when the system is synchronous, the signatures are linerly independent and the first stage of the receiver is a decorrelator. The issue of blind adaptive receiver implementation is also considered, and implementations of the proposed receiver based on the LMS algorithm, the RLS algorithm and subspace-tracking algorithms are presented. These adaptive receivers do not rely on any knowledge on the out-of group users' signals, and are thus particularly suited for rejection of out-of-cell interference in the base station. Simulation results confirm that the proposed structure achieves very satisfactory performance in comparison with previously derived receivers, as well as that the proposed blind adaptive algorithms achieve satisfactory performance.

• Journal of Power Electronics
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• 제10권2호
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• 반도체디스플레이기술학회지
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• 제23권2호
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• pp.76-81
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• 2024

UC Berkeley developed RISC-V, which is an open-source Instruction Set Architecture. This paper proposes a 32-bit 6-stage pipeline architecture based on the RV32I RSIC-V. The performance of the proposed 6-stage pipeline architecture is compared with the existing 32-bit 5-stage pipeline architecture also based on the RV32I processor ISA to determine the impact of the number of pipeline stages on performance. The RISC-V processor is designed in Verilog-HDL and implemented using Quartus Prime 20.1. To compare performance the Dhrystone benchmark is used. Subsequently, peripherals such as GPIO, TIMER, and UART are connected to verify operation through an FPGA. The maximum clock frequency for the 5-stage pipeline processor is 42.02 MHz, while for the 6-stage pipeline processor, it was 49.9MHz, representing an 18.75% increase.

• 한국환경농학회지
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• 제38권1호
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• pp.47-53
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• 2019

BACKGROUND: This experiment was conducted to examine the effects of organic Se concentration and the number of foliar applications on growth characteristics and Se content in rice. METHODS AND RESULTS: A series of multiple foliar applications were performed at (1) 3 times (maximum tillering stage + booting stage + heading stage), (2) 4 times I (effective tillering stage + maximum tillering stage + booting stage + heading stage), (3) 4 times II (maximum tillering stage + booting stage + heading stage + grain filling stage) according to the development stage. Each set of the foliar application plots was treated with 0, 10, 20, 40, 60, 100 ppm of Se and with mixed pesticide ($P^*$ + Se 40 ppm) in which the treatment time was the same as that of the treatment 4 times II. The total cultivation period of rice was 184 days. Se contents in rice (brown rice, white rice) were analyzed by ICP. CONCLUSION: The number of grains per head tended to decrease with increasing concentrations of organic Se in all treatments. However, number of panicles per hill did not show statically significant differences between the 3 times and 4 times I treatments. The grain yield decreased with the 3 times and 4 times II, but there was no significant difference in 4 times I. Se content in brown rice was the highest at 100 ppm Se (5268.64) treatment and lowest at 10 ppm Se ($1269.19{\mu}g{\cdot}kg^{-1}$) treatment. Se content in the polished rice was the highest at 100 ppm Se (5047.33) treatment and lowest at 10 ppm Se ($885.05{\mu}g{\cdot}kg^{-1}$) treatment. The higher selenium was treated, the higher Se content was found in the rice (brown rice, polished rice).

• 수산해양기술연구
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• 제22권4호
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• pp.75-82
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• 1986

음향집어에 관한 기초자료를 제공하기 위하여 정치망내의 수중환경소음과 방성음의 분포 및 집어효과를 실험, 분석하였고, 그 결과를 요약하면 다음과 같다. 1. 수중환경 소음 및 방성음의 중심주파수대는 각각 150Hz~400Hz, 400Hz~1000Hz이고, 음압준위는 원통, 헛통, 장등, 비탈그물의 순으로 , 비탈그물, 원통, 헛통, 장등의 순으로 각각 높았다. 양망작업중의 수중소음은 양망개시후 시간의 경과에 따라 음압준위가 높아지나 양망의 마무리 단계에서는 오히려 낮아졌다. 2. 본 실험에서 제작한 방성장치로서 정치망어포부내에 방성한 결과, 초기에는 어군이 방성기주변으로 모여드는 반응을 나타내었으나, 약 30분이 경과하면서 이러한 반응은 약화되었다. 그리고 방성시간과 휴지시간의 간격보다는 방성음압에 군락이 더 민감하였다. 3. 일본에서 제작된 음향집어기(Dainy 0-8)로 해상에서 방성시험을 하여 본 결과, 대체로 방성개시후 약 20분에 어군이 모여들고 방성을 멈추면 곧 흩어졌다. 유집된 어군은 선박교통소음의 환경을 많이 받는 것으로 나타났다. 정치망입구 근처의 장등에 음향집어기를 설치하여 방성하였을 경우와 방성하지 않았을 경우에 대한 어획량이 방성하지 않았을 때에 비하여 약 3~5배 많은 것으로 나타났다.