• 한국초전도ㆍ저온공학회논문지
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• 제17권1호
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• pp.14-16
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• 2015

Due to the considerable development of the technology of second generation high-temperature superconductors and a significant improvement in their mechanical and transport properties in the last few years it is possible to use HTS tapes in the magnetic levitation systems. The advantages of tapes on a metal substrate as compared with bulk YBCO material primarily in the strength, and the possibility of optimizing the convenience of manufacturing elements of levitation systems. In the present report presents the results of the magnetic levitation force measurements between the stack of HTS tapes containing $n=2{\div}200$ of tapes $12mm{\times}12mm$ and NdFeB permanent magnet in the FC and ZFC regimes. It was found a non- linear dependence of the levitation force from the height of the array of stack in both modes: linear growth at small thickness gives way to flattening and constant at large number of tapes in the stack. Established that the levitation force of stacks comparable to that of bulk samples. The numerical calculations using finite element method showed that without the screening of the applied field the levitation force of the bulk superconductor and the layered superconductor stack with a critical current of tapes increased by the filling factor is exactly the same, and taking into account the screening force slightly different.

• 한국수소및신에너지학회논문집
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• 제23권1호
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• pp.8-18
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• 2012

This paper presents a three-dimensional, transient cold-start polymer electrolyte fuel cell (PEFC) model to numerically evaluate the effects of membrane electrode assembly (MEA) design and cell location in a PEFC stack on PEFC cold start behaviors. The cold-start simulations show that the end cell experiences significant heat loss to the sub-freezing ambient and thus finally cold-start failure due to considerable ice filling in the cathode catalyst layer. On the other hand, the middle cells in the stack successfully start from $-30^{\circ}C$ sub-freezing temperature due to rapid cell temperature rise owing to the efficient use of waste heat generated during the cold-start. In addition, the simulation results clearly indicate that the cathode catalyst layer (CL) composition and thickness have an substantial influence on PEFC cold-start behaviors while membrane thickness has limited effect mainly due to inefficient water absorption and transport capability at subzero temperatures.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.95-97
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• 2005

Loss in the multi-stacked HTS wires are affected by a number of factor, such as, number of wires used in the stack, direction of external magnetic field and insulation thickness between the wire. This paper examines the effects of the insulation thickness on the magnetization loss of the multi-stacked YBCO coated conductor. Measurements of magnetization loss were performed using 4 different typo of multi-stacked wires and under various angle of external magnetic field. Test results show that loss density per unit volume increased for YBCO coated conductors when thickness of insulation increased. Loss density per unit volume decreased for YBCO coaled conductors when stacking number of tapes increased.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• Applied Microscopy
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• 제46권2호
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• pp.93-99
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• 2016

The thickness of specimen is an important factor in microscopic researches. Thicker specimen contains more information, but it is difficult to obtain well focused image with precise details due to optical limit of conventional microscope. Recently, a microscope unit that combines improved illumination system, which allows real time three-dimensional (3D) image and automatic z-stack merging software. In this research, we evaluated the usefulness of this unit in observing thick samples; Golgi stained nervous tissue and ground prepared bone, tooth, and non-transparent small sample; zebra fish teeth. Well focused image in thick samples was obtained by processing z-stack images with Panfocal software. A clear feature of neuronal dendrite branching pattern could be taken. 3D features were clearly observed by oblique illumination. Furthermore, 3D array and shape of zebra fish teeth was clearly distinguished. A novel combination of two channel oblique illumination and z-stack imaging process increased depth of field and optimized contrast, which has a potential to be further applied in the field of neuroscience, hard tissue biology, and analysis of small organic structures such as ear ossicles and zebra fish teeth.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.115-121
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• 2002

In this research we have investigated the characteristics of ultra thin $HfO_2 /SiON$stack structure films using several analytical techniques. SiON layer was thermally grown on standard SCI cleaned silicon wafer at $825^{\circ}C$ for 12sec under $N_2$O ambient. $HfO_2 /SiON$$_4$/$H_2O$ as precursors and $N_2$as a carrier/purge gas. Solid HfCl$_4$was volatilized in a canister kept at $200^{\circ}C$ and carried into the reaction chamber with pure $N_2$carrier gas. $H_2O$ canister was kept at $12^{\circ}C$ and carrier gas was not used. The films were grown on 8-inch (100) p-type Silicon wafer at the $300^{\circ}C$ temperature after standard SCI cleaning, Spectroscopic ellipsometer and TEM were used to investigate the initial growth mechanism, microstructure and thickness. The electrical properties of the film were measured and compared with the physical/chemical properties. The effects of heat treatment was discussed.

• 반도체디스플레이기술학회지
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• 제8권1호
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• pp.13-17
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• 2009

In PRAM applications, the devices can be made for both binary and multi-state storage. The ability to attain intermediate stages comes either from the fact that some chalcogenide materials can exist in configurations that range from completely amorphous to completely crystalline or from designing device structure such a way that mimics multiple phase chase phenomena in single cell. We have designed stack-structured phase change memory cell which operates as multi-state storage. Amorphous $Ge_xTe_{100-x}$ chalcogenide materials were stacked and a diffusion barrier was chosen for each stack layers. The device is operated by crystallizing each chalcogenide material as sequential manner from the bottom layer to the top layer. The amplitude of current pulse and the duration of pulse width was fixed and number of pulses were controlled to change overall resistance of the phase change memory cell. To optimize operational performance the thickness of each chalcogenide was controlled based on simulation results.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.164-164
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• 2009

A multilayer piezoelectric transformer(MPT) for step-down voltage was made by ceramic stack process. And then, the characteristics of piezoelectric transformer, such as resonance frequency, matching impedance, electro-mechanical coupling coefficient, voltage gain, heat generation and efficiency, are analyzed. The piezoelectric transformer consists of a lead zirconate titanate ceramic with a high electromechanical quality factor. The piezoelectric transformer, with a multilayered construction in the thickness direction, was formed with dimensions 15mm long, 15mm wide and 5mm thick.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.500-510
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• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.