• Journal of Computing Science and Engineering
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• 제8권4호
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권5호
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• pp.218-225
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• 2001

This paper analyses the performance of network system using the CAN(Controller Area Network) protocol. Given messages are assumed to be scheduled by the DMS(Deadline Monotonic Scheduling) algorithm. The mathematical models for time-delay that can be occurred between CAN nodes are defined. The effectiveness of modeling is shown by comparing the difference of time-delay between simulations and practical experiments. We analyse the results according to the variation of factors, such as the number of nodes, the transmission speed, the message size and the number of aperiodic messages through simulation and confirm the real-time performance of lower priority messages. We also investigate the real-time performance of periodic messages when aperiodic message generates.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송∙미디어공학회 2017년도 하계학술대회
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• pp.213-214
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• 2017

홀로그램을 생성하기 위해서 많은 양의 계산을 필요하기 때문에 고속 홀로그램 생성 방법이 필요하다. 본 논문에서는 다중 프로세서와 다중 GPGPU의 스케줄링을 이용하여 고속화 하는 방법을 제안하고 구현하였다. 다중 프로세서를 이용하여 입력과 출력부분을 나누어 동기화 동작을 줄이고, 버퍼를 이용하여 커널과 커널 사이의 대기 시간을 줄일 수 있도록 스케줄링 하였다. nVidia사의 GTX680(Kepler구조) 2개를 이용하여 구현하였을 때, 이전 연구에서 제안한 방법에 비하여 약 70% 정도 계산시간을 줄일 수 있다.

• 한국정보처리학회논문지
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• 제2권1호
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• pp.106-118
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• 1995

본 연구에서는 스케쥴링과 하드웨어 할당에 관련된 상위단계합성에서 최적설계 방법론을 효과적으로 변형된 시뮬레이티드 어닐링 기법을 사용하여 정립한다. 또한 정립된 기법을 디지탈필터(DF : digital filter)의 설계에 적용하여 파이프라인 DF 의 경우 최적설계시에 속도와 하드웨어의 최적의 절충 문제와 어레이 DF에서의 해석 에 관련된 문제점을 검토한다. 이러한 적용사례를 통해 제안된 방법이 보다 빠른 시간 에 향상된 비용함수값을 줄 수 있음이 확인되고 복잡한 디지탈필터 설계에 이용될 수 있음이 입증된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1165-1168
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• 2001

The effect of sensor faults in DTC based induction motor drives is analyzed and a fault detection problem is treated. An adaptive gain scheduling observer is proposed for the design of DTC controller and a fault detection system. The observer provides not only the estimate of stator flux, a key variable in DTC system, but also the estimates of stator current, rotor speed that are useful for fault detection purpose. Simulations for various type of sensor faults are performed to evaluate the performance of the overall control system and the proposed sensor fault detection scheme.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 A
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• pp.858-860
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• 2005

This paper presents an Optimal Power Flow (OPF) algorithm using Interior Point Method (IPM) to swiftly and precisely perform the five minute dispatch. This newly suggested methodology is based on Affine Scailing Interior Point Method (AS IPM), which is favorable for large-scale problems involving many constraints. It is also eligible for OPF problems in order to improve the calculation speed and the preciseness of its resultant solutions. Lastly, this paper provides a relevant case study to confirm the efficiency of the proposed methodology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.2489-2491
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• 2005

Currently, Programmable Logic Contorller(PLC) uses Real Time Operation System(RTOS) as basic OS. RTOS executes defined results as to defined time. General features of RTOS emphasize the priority in each task, high-speed process of external interrupt, task scheduling, synchronization in task, the limitation of memory capacity. For safety critical placement, PLC software needs Verification and Validation(V&V). For example, nuclear power plant. In this paper, PLC RTOS is verified by formal methods. Particularly, formal method V&V uses verification tool called 'STATEMATE', and shows the results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.125-128
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• 2002

This paper designed a cipher process, which used SEED-Algorithm that is totally domestic technique. This cipher processor is implemented by using SEED-cipher-Algorithm and pipeline scheduling architecture. The cipher is 16-round Feistel architecture but we show just 16-round Feistel architecture for brevity in this thesis. Of course, we can get the result of the 16-round processing by addition of control part simply. Furthermore, it has pipelined architecture, so the speed of cipher process is the faster than others when we performed a cipher a lot of data. The schedule-function can performed the two-cipher process simultaneously, such as using two-cipher processors.

• ETRI Journal
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• 제28권1호
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2007년도 춘계학술대회 논문집
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• pp.1481-1498
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• 2007

As railroad industry face the new Renaissance era, effective and efficient maintenance methods for rolling stock operation are required with advanced railroad technology. All kinds of railroad systems such as high speed long distance train, metropolitan mass transit and light rail require systematic maintenance technology in order to maintain the safe railroad operation. Simulation models for detailed operations of the sample maintenance center are developed. In this study, standard maintenance procedures, layout, equipments and number of workers of Siheung Metropolitan Railroad Maintenance Rolling Stock Depot are considered. The proposed simulation models are developed using simulation package ARENA. Three simulation analysis using the developed simulation model are done. First, the bottleneck operation is identified. Second, the relationship between maintenance center size, number of workers and cycle time is analyzed. Lastly, the scheduling performances between PERT/CPM and Critical Chain Project Management(CCPM) are compared.