• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.16-24
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• 2010

High Speed Uplink Packet Access(HSUPA) is a WCDMA Release 6 technology which corresponds to High Speed Downlink Packet Access(HSDPA). Node B Supports fast scheduling, Hybrid ARQ(HARQ), short Transmission Time Interval(TTI) for high rate uplink packet data. It is very important to detect Iub congestion to improve end user's Quality of Service(QoS). This paper proposes Node B Congestion Detection(BCD) mechanism and suggests to use the hybrid of Transport Network Layer(TNL) congestion detection and BCD. It is shown that HSUPA user throughput performance can be improved by the proposed method even with small Iub bandwidth.

• Journal of Information Processing Systems
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• v.18 no.3
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• pp.428-442
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• 2022

A reliable automatic passenger counting (APC) system is a key point in transportation related to the efficient scheduling and management of transport routes. In this study, we introduce a lightweight head detection network using deep learning applicable to an embedded system. Currently, object detection algorithms using deep learning have been found to be successful. However, these algorithms essentially need a graphics processing unit (GPU) to make them performable in real-time. So, we modify a Tiny-YOLOv3 network using certain techniques to speed up the proposed network and to make it more accurate in a non-GPU environment. Finally, we introduce an APC system, which is performable in real-time on embedded systems, using the proposed head detection algorithm. We implement and test the proposed APC system on a Samsung ARTIK 710 board. The experimental results on three public head datasets reflect the detection accuracy and efficiency of the proposed head detection network against Tiny-YOLOv3. Moreover, to test the proposed APC system, we measured the accuracy and recognition speed by repeating 50 instances of entering and 50 instances of exiting. These experimental results showed 99% accuracy and a 0.041-second recognition speed despite the fact that only the CPU was used.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.20-29
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• 2014

Recently, LTE is preparing to make a new leap forward LTE-A all over the world. As LTE privides high speed service, the role of mobile phones seems to change from voice to data service. According to Cisco, global mobile data traffic will increase nearly 11-fold between 2013 and 2018. Mobile video traffic will reach 75% by 2018 from 66% in 2013 in Korea. However, voice service is still the most important role of mobile phones. Thus, controllability of throughput and low BLER is indispensable for high-quality VoIP service among various type of traffic. Although the maximum AMR-WB, 23.85 Kbps is sufficient to a VoIP call, it is difficult for the LTE which can provide tens to hundreds of MB/s may not keep the certain level VoIP QoS especially in the cell-edge area. This paper proposes a new scheduling algorithm in order to improve VoIP performance after analyzing various scheduling algorithms. The proposal is the technology which applies more priority processing for VoIP than other applications in cell-edge area based on two-tier scheduling algorithm. The simulation result shows the improvement of VoIP performance in the view point of throughput and BLER.

• Journal of Internet of Things and Convergence
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• v.10 no.3
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• pp.19-24
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• 2024

Recent advances in large-scale data processing technologies such as big data, cloud computing, and artificial intelligence have increased the demand for high-performance storage devices in data centers and enterprise environments. In particular, the fast data response speed of storage devices is a key factor that determines the overall system performance. Solid state drives (SSDs) based on the Non-Volatile Memory Express (NVMe) interface are gaining traction, but new bottlenecks are emerging in the process of handling large data input and output requests from multiple hosts simultaneously. SSDs typically process host requests by sequentially stacking them in an internal queue. When long transfer length requests are processed first, shorter requests wait longer, increasing the average response time. To solve this problem, data transfer timeout and data partitioning methods have been proposed, but they do not provide a fundamental solution. In this paper, we propose a dual queue based scheduling scheme (DQBS), which manages the data transfer order based on the request order in one queue and the transfer length in the other queue. Then, the request time and transmission length are comprehensively considered to determine the efficient data transmission order. This enables the balanced processing of long and short requests, thus reducing the overall average response time. The simulation results show that the proposed method outperforms the existing sequential processing method. This study presents a scheduling technique that maximizes data transfer efficiency in a high-performance SSD environment, which is expected to contribute to the development of next-generation high-performance storage systems

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.218-224
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• 2001

The objective of Distributed Parallel Computing is to solve the computationally intensive problems, which have several types of parallelism, on a suite of high performance and parallel machines in a manner that best utilizes the capabilities of each machine. In this paper, we propose a computational model including the generalized graph representation method of distributed parallel systems for speedup analysis, and analyze how the super-linear speedup is achieved when scheduling of programs with diverse embedded parallelism modes onto a distributed heterogeneous supercomputing network environment. The proposed representation method can also be applied to simple homogeneous or heterogeneous systems whose components are heterogeneous only in terms of the processor speed. In order to obtain the core speedup, the matching of the parallelism characteristics between tasks and parallel machines should be carefully handled while minimizing the communication overhead.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.11
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• pp.575-582
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• 2001

This paper presents a calculating method of switching angle for adaptive switched reluctance motor (SRM) drive of a drill. The operation of the SRM is completely characterized by the flux linked by one phase winding which depends only on the current in that same phase winding and the rotor position. An efficiently adaptive SRM drive is possible on appropriately scheduling the commutation angles with accurate rotor position, supplied current value and speed information. An adaptive SRM drive with reduction torque ripple should be controlled by an optimized phase current control along with rotor position. Therefore, we are suggested a computing method of switching turn-on and off angles for adaptationally SRM operation with varied rotor speed and load. To probe the computing method, we have some simulation and experiment, it is shown a good result that can be computing the optimized switching angles for an electric drill motor.

• Journal of the Korea Safety Management & Science
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• v.4 no.1
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• pp.105-114
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• 2002

Nowadays, most companies seek after the greatest profit by means of offering the goods which consumers want timely and efficiently and minimizing the cost of inventory and distribution channel which amounts to the great portion of total cost. And according as EC(Electronic Commerce) market has increased rapidly, SCM(Supply Chain Management) for EC become one of the most important facts for companies, therefore this paper suggest SCM scheme which EC, especially B to C, is added to the existing commerce system. This paper uses internet for information integration of distribution channel which is away from one another and applies TOC(Theory of Constraint)'s DBR(Drum-Buffer-Rope) Scheduling for synchronization through the whole supply chain. It is possible to synchronize the whole supply chain by means of making the speed of manufacturing and distribution to be controlled by consumer's order which is received in distribution center, and inventory and loss of sales opportunities are minimized by constant. Buffer Management. If inventories in distribution center is short, then it needs to search CCR(Capacity Constraint Resource) in supply chain and to control the speed of manufacturing and distribution according to the ability of CCR. This paper applies PT(Partial Transshipment) strategy for Delivery from distribution center to store or cyber consumer. the strategy this paper suggests chooses neighbour area from area which each distribution center takes charge, and then makes product ordered by cyber consumer which lives in the chosen area to be delivered according to inventory of distribution center.

• International conference on construction engineering and project management
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• 2015.10a
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• pp.328-332
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• 2015

By logging position data from GPS-equipped construction machines, we re-create daily activities as 3D animations to analyze performance and facilitate look-ahead scheduling. The 3D animation enables going back to any point in time and space to observe the activities as they took place. By segmenting data into a set of activities, it is possible to obtain actual measures of performance such as cycle times, production, speed profiles and idle times. The measures of performance can then be compared to those expected (e.g., theoretical speed profiles vs. observed profiles), and instances of significant difference can be flagged for further investigation. Idle times and queues that exceed prescribed thresholds can also be identified. In general, many of the traditional real-time performance analyses can be performed after the fact. Situations of interest can be identified automatically and the events in this manner enhances effective performance improvement in construction. The proposed research is explained and demonstrated using a real push-loaded earthmoving operation.

• Management Science and Financial Engineering
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• v.4 no.2
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• pp.43-58
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• 1998

Packet switch is a key component in high speed digital networks. This paper investigates congestion phenomena in the packet switching with input buffers. For large value of switch size N, mathematical models have been developed to analyze asymptotic maximum switch throughput under nonuniform traffic. Simulation study has also been done for small values of finite N. The rapid convergence of the switch performance with finite switch size to asymptotic solutions implies that asymptotic analytical solutions approximate very closely to maximum throughputs for reasonably large but finite N. Numerical examples show that non-uniformity in traffic pattern could result in serious degradation in packet switch performance, while the maximum switch throughput is 0.586 when the traffic load is uniform over the output trunks. Window scheduling policy seems to work only when the traffic is relatively uniformly distributed. As traffic non-uniformity increases, the effect of window size on throughput is getting mediocre.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.643-646
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• 2005

This paper presents CARMA (Cycle-Accurate Retargetable Micro-Architecture) as efficient framework for SoC-centric pipelined instruction-set architectures. It is based on ADL (Architecture Description Language) and provides more concise and manifest semantics to describe behavior of instruction set by mixing efficiency of instruction-set simulators and flexibility of RTL simulators. It exploits new timing model method based on process scheduling so it can support general timing model with cycle accuracy for large-scaled architectures usually used in SoC multimedia chip-set. According to experiments, the proposed framework was shown to be 5.5 times faster than HDL and 2.5 times faster than System-C in simulation speed so it is applicable for complex instruction-set pipelined architectures.