• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.79-85
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• 2018

This paper presents an implementation method of Long Term Evolution-Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a general-purpose multicore Digital Signal Processor (DSP), TMS320C6670. Although the DSP provides some useful coprocessors such as turbo decoder, fast Fourier transformer, Viterbi Coprocessor, Bit Rate Coprocessor etc., it is specific to the base station platform implementation not the mobile terminal platform implementation. This paper shows an implementation method of the LTE-A PDSCH decoder using programmable DSP cores as well as the coprocessors of Fast Fourier Transformer and turbo decoder. First, it uses the coprocessor supported by the TMS320C6670, which can be used for PDSCH implementation. Second, we propose a core programming method using DSP optimization method for block diagram of PDSCH that can not use coprocessor. Through the implementation, we have verified a real-time decoding feasibility for the LTE-A downlink physical channel using test vectors which have been generated from LTE-A Reference Measurement Channel (RMC) Waveform R.6.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.401-407
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• 2000

Modern microprocessors exploit instruction-level parallel processing to increase the performance. Especially VLIW processors supported by the parallelizing compiler are used more and more in specific applications such as high-end DSP and graphic processing. Bus-based VLIW architecture was proposed for these specific applications and it was designed to reduce the overhead of forwarding unit and the instruction width. In this paper, a optimizing scheduling compiler developed for the proposed bus-based VLIW processor is introduced. First, the method to model interconnections between buses and resource usage patterns is described. Then, on the basis of the modeling, machine-dependent optimization techniques such as bus-to-register promotion, copy coalescing and operand substitution were implemented. Optimization techniques for general-purpose VLIW microprocessors such as selective scheduling and enhanced pipelining scheduling(EPS) were also implemented. The experiment result shows about 20% performance gain for multimedia application benchmarks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.66-76
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• 2000

This paper describes design and implementation of caption-processing ASIC(Application Specific Integrated Circuits) for OSD(On Screen Display) of karaoke system. The OSD of conventional karaoke system was implemented by a general purpose DSP, however this paper suggest a design to save hardware resources. The ASIC receives commands and data of graphic and caption from host processor, and then modifies the data to have various graphic effects. The design has been done by schematic and VHDL coding. The design was verified by logic simulation and FPGA emulation on the real system. The chip was fabricated with 0.8${\mu}{\textrm}{m}$ CMOS SOG, and worked properly at the karaoke system.

• Journal of Biosystems Engineering
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• v.43 no.4
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• pp.426-439
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• 2018

Purpose: To continuously monitor soil and climatic properties, a data acquisition system (DAQ) was developed and tested in plum farms (Gyewol-ri and Haechang-ri, Suncheon, Korea). Methods: The DAQ consisted of a Raspberry-Pi processor, a modem, and an ADC board with multiple sensors (soil moisture content (SEN0193), soil temperature (DS18B20), climatic temperature and humidity (DHT22), and rainfall gauge (TR-525M)). In the laboratory, various tests were conducted to calibrate SEN0193 at different soil moistures, soil temperatures, depths, and bulk densities. For performance comparison of the SEN0193 sensor, two commercial moisture sensors (SMS-BTA and WT-1000B) were tested in the field. The collected field data in Raspberry-Pi were transmitted and stored on a web server database through a commercial communications wireless network. Results: In laboratory tests, it was found that the SEN0193 sensor voltage reading increased significantly with an increase in soil bulk density. A linear calibration equation was developed between voltage and soil moisture content depending on the farm soil bulk density. In field tests, the SEN0193 sensor showed linearity (R = 0.76 and 0.73) between output voltage and moisture content; however, the other two sensors showed no linearity, indicating that site-specific calibration is important for accurate sensing. In the long-term monitoring results, it was observed that the measured climate temperature was almost the same as website information. Soil temperature information was higher than the values measured by DS18B20 during spring and summer. However, the local rainfall measured using TR 525M was significantly different from the values on the website. Conclusion: Based on the test results obtained using the developed monitoring system, it is thought that the measurement of various parameters using one device would be helpful in monitoring plum growth. Field data from the local farm monitoring system can be coupled with website information from the weather station and used more efficiently.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.3 no.4
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• pp.95-107
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• 1983

The general purpose programs are in their fixed algorithm and theory of mechanics which can not be altered without painful program modifications. Users are usually guided by user's manual for data input. The several symbolic manipulation programs for structural analysis are introduced recently. These programs allow users to include a wide class of solution algorithm and to specify, by means of some symbolic manipulation, a combination of analytical steps to suit a particular problem. As they can solve a single domain problem, a large computer is usually needed. The scope of this study is to develop an efficient symbolic manipulation program with space beam element, plate bending element and eigen value routines. The incorporated Substructure capability and generation capability of finite element characteristic arrays (e.g., stiffness matrix, mass matrix) enables users to analyse multidomain problem with small computer. The program consists of modulized independent processors, each having its own specific function and is easily modified, eliminated and added. The processors are efficiently handling data by the Data base approach which is the concept of integrated program network(IPN).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.659-666
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• 2006

Servo-motors are used as key components of automated system by performing precise motion control as accurate positioning and accurate speed regulation in response to the commands from computers and sensors. Especially, the linear brushless servo-motors have numerous advantages over the rotary servo motors which have connection with the friction induced transfer mechanism such as ball screws, timing belts, rack/pinion. This paper proposes an estimation method of unknown motor system parameters using the informations from the sinusoidal driving type linear brushless DC motor dynamics and outputs. The estimated parameters can be used to tune the controller gain and a disturbance observer. In order to meet this purpose high performance Digital Signal Processor, TMS320F240, designed originally for implementation of a Field Oriented Control(FOC) technology is adopted as a controller of the liner BLDC servo motor. Having A/D converters, PWM generators, rich I/O port internally, this servo motor application specific DSP play an important role in servo motor controller. This linear BLDC servo motor system also contains IPM(Intelligent Power Module) driver and hail sensor type current sensor module, photocoupler module for isolation of gate signals and fault signals.