• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.195-198
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.216-226
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• 1989

In this paper, we explain about an outline of the decoding method for double encoding system using the error correcting capacitance and a simple decoding method. We have been taken formation two-dimension code word of doubly-encoded code using $C_1$(32, 28, 5) and $C_2$(32, 26, 7) Reed-Solomon codes, and had computer simulation of the erroe correcting processes in frequency domain. On these processes, the newly developed digital signal processing technology such as error correction using Berlekamp-Massey algorithm in frequency domain have been proven.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4C
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• pp.191-196
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• 2011

In this paper, we propose a design method of Reed-Solomon (23, 17) decoder for UWB using direct decoding method. The direct decoding algorithm is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 $GF(2^m)$ multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders need about 20 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.557-560
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• 2014

In digital communications systems, an interleaver spreads burst errors occurred in channels and makes it random errors. As a result, the signals are rearranged and encrypted to the 3rd party. Deinterleaving this unknown interleaved signal is very important in electronic warfare and various researches on reconstruction of interleaved signal have been studied in the literature. Unlike previous researches which is mainly about helical scan interleaver or bit unit interleaver, in this paper, we estimate the symbol unit convolutional interleavr and shortened Reed-Solomon code parameters such as the number of stages of interleaver, a codeword length and a data symbol length and propose an specific algorithm to obtain the parameters from the unknown interleaved signal and simulate this algorithm as well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.659-664
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• 2006

We propose two error correcting algorithms for high-density optical storage systems. The first algorithm reduces the false-erasure declaration by reducing the sensitivity on random errors and increases the code rate using a simple erasure indication method. The second one exploits just the known indicator flag instead of error correcting code such as Reed-Solomon(RS) code. The proposed algorithms are superior to the error correcting algorithms of conventional systems such as DVD and BD.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.9
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• pp.3870-3884
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• 2020

The proposed framework of Four Layer Robust Storage in Cloud (FLRSC) architecture involves host server, local host and edge devices in addition to Virtual Machine Monitoring (VMM). The goal is to protect the privacy of stored data at edge devices. The computational intelligence (CI) part of our algorithm distributes blocks of data to three different layers by partially encoded and forwarded for decoding to the next layer using hash and greed Solomon algorithms. VMM monitoring uses snapshot algorithm to detect intrusion. The proposed system is compared with Tiang Wang method to validate efficiency of data transfer with security. Hence, security is proven against the indexed efficiency. It is an important study to integrate communication between local host software and nearer edge devices through different channels by verifying snapshot using lamport mechanism to ensure integrity and security at software level thereby reducing the latency. It also provides thorough knowledge and understanding about data communication at software level with VMM. The performance evaluation and feasibility study of security in FLRSC against three-layered approach is proven over 2³² blocks of data with 98% accuracy. Practical implications and contributions to the growing knowledge base are highlighted along with directions for further research.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.549-552
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• 2003

In this paper, an efficient architecture of a versatile Reed-Solomon (RS) decoder is designed, where the message length k as well as the block length n can be variable. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm(MEA). A new architecture for the MEA is designed for variable values of error correcting capability t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive and the overclocking technique. The decoder can decode a codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications due to its versatility. A versatile RS decoder over GF(2$^{8}$ ) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.