• Journal of Digital Contents Society
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• v.12 no.2
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• pp.141-150
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• 2011

Recently the Solid State Drive (SSD) is widely used for storage system of various mobile devices. In this case, existing buffer replacement algorithms based on the hard disk do not consider characteristics of flash memory, so it caused performance degradation of the system. This paper proposes a novel buffer replacement policy called ABM (Asymmetric Buffer Management) policy. ABM policy separates read and write buffer space and applies different replacement unit and replacement algorithm for each buffer. In addition, write buffer delay scheme and dynamic size adaptation algorithm is applied for better performance. ABM outperforms other replacement policies, especially ABM-LRU-CLC shows 32% better performance than normal LRU policy.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.467-470
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• 2004

Diamond-Like Carbon (DLC) thin film is a semiconductor with high mechanical hardness, low friction coefficient, high chemical inertness, and optical transparency. DLC thin films have widespread applications as protective coatings and solid lubricant coatings in areas such as Hard Disk Drive (HDD) and Micro-Electro-Mechanical-Systems (MEMS). In this work, the wear characteristics of DLC thin films deposited on silicon substrates using a DC-magnetron sputtering system were analyzed. The wear tracks were measured with an Atomic Force Microscope (AFM). To identify the sp2 and sp3 hybridization of carbon bonds and other bonds Raman spectroscopy was used. The structural information of DLC thin films was obtained with Fourier transform infrared spectroscopy and wear tests were conducted by using a micro-pin-on-reciprocator tester. Results showed that the wear characteristics were dependent on the sputtering conditions. The wear rate could be correlated with the bonding state of the DLC thin film.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.365-370
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• 2004

The integration of intelligent devices, devices-level networks, and software into motor control systems can deliver improved diagnostics, fast warnings for increased system reliability, design flexibility, and simplified wiring. Remote access to motor-control information also affords an opportunity for reduced exposure to hazardous voltage and improved personnel safety during startup and trouble-shooting. This paper presents LonWorks fieldbus networked intelligent induction control system architecture. Experimental bed system with two inverter motor driving system for controlling 1.5kW induction motor is configured for LonWorks networked intelligent motor control. In recent years, MCCs have evolved to include component technologies, such as variable-speed drives, solid-state starters, and electronic overload relays. Integration was accomplished through hardwiring to a programmable logic controller (PLC) or distributed control system (DCS). Devicelevel communication networks brought new possibilities for advanced monitoring, control and diagnostics. This LonWorks network offered the opportunity for greatly simplified wiring, eliminating the bundles of control interwiring and corresponding complex interwiring diagrams. An intelligent MCC connected in device level control network proves users with significant new information for preventing or minimizing downtime. This information includes warnings of abnormal operation, identification of trip causes, automated logging of events, and electronic documentation. In order to show the application of the multi-motors control system, the prototype control system is implemented. This paper is the first step to drive multi-motors with serial communication which can satisfy the real time operation using LonWorks network.

• KIISE Transactions on Computing Practices
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• v.23 no.6
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• pp.379-385
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• 2017

In enterprise environments, hybrid storage typically utilizes SSDs over disk-based RAID. Typically, SSDs over RAID are used as the data cache. Recently, the LeavO caching scheme was introduced to reduce the parity update overhead of the underlying RAID. In this paper, we combine the data caching and LeavO caching schemes and derive cost models of the combined cache to determine the optimal data and LeavO cache sizes. We also propose the Adaptive Combined Cache that dynamically adjusts the data cache and LeavO cache sizes for evolving workloads. Experimental results show that the performance of the Adaptive Combined Cache is significantly superior to that of the conventional data caching scheme and is comparable with that of the off-line optimal scheme.

• Journal of the Semiconductor & Display Technology
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• v.7 no.3
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• pp.17-21
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• 2008

Application of flash memory in mobile and ubiquitous related devices is rapidly being increased due to its low price and high performance. In addition, some notebook computers currently come out into market with a SSD(Solid State Disk) instead of hard-drive based storage system. Regarding this trend, applications need to increase the storage capacity using multiple flash memory chips for larger capacity sooner or later. Flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its physical property. In order to make flash memory storage work with tangible performance, reclaiming of invalid regions needs to be controlled in a particular manner to decrease the number of erasures and to distribute the erasures uniformly over the whole memory space as much as possible. In this paper, we study the performance of flash memory recycling algorithms and demonstrate that the proposed algorithm shows acceptable performance for flash memory storage with multiple chips. The proposed cleaning method partitions the memory space into candidate memory regions, to be reclaimed as free, by utilizing threshold values. The proposed algorithm handles the storage system in multi-layered style. The impact of the proposed policies is evaluated through a number of experiments.

• Proceedings of the SAREK Conference
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• 2009.06a
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• pp.1379-1384
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• 2009

High power light emitting diode(LEDs), a strong candidate for the next generation general illumination applications are of interest. With major advantages of power saving, increased life expectancy and faster response time over traditional incandescent bulb, the LEDs are rapidly taking over many applications such as LCD backlighting, traffic light, automotive lighting, signage, etc. The increased electrical currents used to drive the LEDs have focused more attention on the thermal management because the efficiency and reliability of the solid-state lighting devices strongly depend on successful thermal management. There exist some problems that are caused by heat generation in the LED package, such as wire breakage, yellowing of epoxy resin, lifted chip caused by reflow of thermal paste chip attach and interfacial separation between LED package and silicon resin. The goal of this study is to analyze high power LED thermal properties of using pulsating heat pipe.

• Journal of KIISE:Databases
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• v.35 no.5
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• pp.400-410
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• 2008

Flash memory has been widely used in mobile devices, such as mobile phone and digital camera. Recently flash SSD(Solid State Disk), having same interface of the disk drive, is replacing the hard disk of some laptop computers. However, flash memory still cannot be considered as the storage of database systems. The FTL(Flash Translation Layer) of commercial flash SSD, making flash memory operate exactly same as a hard disk, shows poor performance on the workload of databases with many random overwrites. Recently In-Page Logging(IPL) approach was proposed to solve this problem. In this paper, we implement IPL approach on SQLite, a popular open source embedded DBMS, and evaluate its performance. It improves the performance by up to 30 factors for update queries.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.6
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• pp.2139-2151
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• 2014

Embedded system testing, especially long-term reliability testing, of flash memory solutions such as embedded multi-media card, secure digital card and solid-state drive involves strategic decision making related to test sample size to achieve high test coverage. The test sample size is the number of flash memory devices used in a test. Earlier, there were physical limitations on the testing period and the number of test devices that could be used. Hence, decisions regarding the sample size depended on the experience of human testers owing to the absence of well-defined standards. Moreover, a lack of understanding of the importance of the sample size resulted in field defects due to unexpected user scenarios. In worst cases, users finally detected these defects after several years. In this paper, we propose that a large number of potential field defects can be detected if an adequately large test sample size is used to target weak features during long-term reliability testing of flash memory solutions. In general, a larger test sample size yields better results. However, owing to the limited availability of physical resources, there is a limit on the test sample size that can be used. In this paper, we address this problem by proposing a self-adaptive reliability testing scheme to decide the sample size for effective long-term reliability testing.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.1-7
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• 2017

As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.377-382
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• 2010

With the advent of flash memory based new storage device (SSD), there is considerable interest within the computer industry in using flash memory based storage devices for many different types of application. The dynamic index structure of large text collections has been a primary issue in the Information Retrieval Applications among them. Previous studies have proven the three approaches to be effective: In- Place, merge-based index structure and a combination of both. The above-mentioned strategies have been researched with the traditional storage device (HDD) which has a constraint on how keep the contiguity of dynamic data. However, in case of the new storage device, we don' have any constraint contiguity problems due to its low access latency time. But, although the new storage device has superiority such as low access latency and improved I/O throughput speeds, it is still not well suited for traditional dynamic index structures because of the poor random write throughput in practical systems. Therefore, using the experimental performance evaluation of various index maintenance schemes on the new storage device, we propose an efficient index structure for new storage device that improves significantly the index maintenance speed without degradation of query performance.