• Bulletin of the Korean Space Science Society
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• 2003.10a
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• pp.62-62
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• 2003

과학위성 1호에는 위성의 임무를 수행하기 위하여 광학계, 구조부, 및 전자부 등 여러가지 부품들이 실장되는데, 그 중 전자부의 가장 중요한 부품 중의 하나인 인쇄회로기판(Printed Circuit Board, PCB)의 우주환경에서의 특성 대해서 논의하고자 한다. Solder Resistor(Solder Mask)의 화학성분이 위성체가 작동하는 우주환경에서 위성체 임무수행 시 발생할 수 있는 out-gassing으로 인해 위성체가 본연의 임무 실패라는 결과를 초래할 수 있다 NASA 및 ESA의 Out-gassing에 관한 규정과 TRW에 의한 KOMSAT에 사용된 재료의 진공상태의 Outgassing에 관한 내용에 의하면, 재료의 진공상태와 Out-gassing은 America Society for Testing and Materials에서 제시한 ASTM E959 기준에 따라 제작된다. 일반적으로 우주 환경에서 광학계나 전자부의 원활한 동작을 위해서는 인쇄 회로 기판의 총 질량손실(Total Mass Loss, TML)은 1.00%을 넘지 말아야 하며, 휘발성 응축 질량 (Collected Volatile Condensable Mass, CVCM)은 0.1% 미만이어야 한다. Total Mass Loss(TML) 방법은 대기중에서 측정한 질량과 진공 조건에서 변화되는 질량을 측정함으로써 진공조건에서의 탈기체 특성을 측정하는 방법이다. 본 연구에서는 Solder Resistor(Solder Mask)의 탈기체 측정을 위한 진공챔버의 측정방법 및 진공 형성 과정을 기술하고 실제 과학위성1호에 장착될 시료를 예로 들어 인쇄회로기판에 입힌 Solder Resistor(Solder Mask)가 우주환경인 진공상태에서 위성체 부품의 작동 시 발생할 수 있는 탈기체되는 정도를 질량의 변화분으로 측정하여 위성체가 우주 환경에서 본연의 임무를 안전하게 수행할 있는지를 검증하였다.부분이다.다.향을 해석하고 시뮬레이션 하였다.Device Controller)는 ECU로부터 명령어를 받아서 arm 및 safe 상태에 대한 텔리 메트리 데이터를 제공한다 그리고, SAR(Solar Array Regulator)는 ECU로부터 Bypass Relay 및 ARM Relay에 관한 명령어를 받아 수행되며 그에 따른 텔리 메트리 데이터를 제공한다. 마지막으로 EPS 소프트웨어를 검증하는 EPS Software Verification을 수행하였다 전력계 소프트웨어의 설계의 검증 부분은 현재 설계 제작된 전력계 .소프트웨어의 동작 특성 이 위성 의 전체 운용개념과 연계하여 전력계 소프트웨어가 전력계 및 위성체의 요구조건을 만족시키는지를 확인하는데 있다. 전력계 운용 소프트웨어는 배터리의 충ㆍ방전을 효율적으로 관리해 3년의 임무 기간동안 위성체에 전력을 공급할 수 있도록 설계되어 있다this hot-core has a mass of 10sR1 which i:s about an order of magnitude larger those obtained by previous studies.previous studies.업순서들의 상관관계를 고려하여 보다 개선된 해를 구하기 위한 연구가 요구된다. 또한, 준비작업비용을 발생시키는 작업장의 작업순서결정에 대해서도 연구를 행하여, 보완작업비용과 준비비용을 고려한 GMMAL 작업순서문제를 해결하기 위한 연구가 수행되어야 할 것이다.로 이루어 져야 할 것이다.태를 보다 효율적으로 증진시킬 수 있는 대안이 마련되어져야 한다고 사료된다.$\ulcorner$순응$\lrcorner$의 범위를 벗어나지 않는다. 그렇기 때문에도 $\ulcorner$순응$\lrcorner$과 $\ulcorner$표현$\lrcorner$의 성격과 형태를 외형상으로

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.1
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• pp.23-29
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• 2003

Stencil is used normally as a mask for solder pasting on pad of a printed circuit board (PCB). The objective of this study is to develop a stencil cutting system and determine the optimal conditions to make good-quality stencil by using a Nd:YAG laser. The effects of process parameters such as laser power, type of mask, gas pressure, cutting speed and pulse duration on the cut edge quality were investigated. In order to analyze the cut surface characteristics (roughness, kerfwidth, dross) optical microscopy, SEM microscopy and roughness measurements were used. As a result, the optimal conditions of cutting process parameters were determined, and the practical feasibility of the proposed system was also examined by using a commercial Gerber file for PCB stencil manufacturing.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.55-65
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• 2020

The use of underfill materials in semiconductor packages is not only important for stress relieving of the package, but also for improving the reliability of the package during shock and vibration. However, in recent years, as the size of the package becomes larger and very thin, the use of the underfill shows adverse effects and rather deteriorates the reliability of the package. To resolve these issues, we developed the package using a solid epoxy material to improve the reliability of the package as a substitute for underfill material. The developed solid epoxy was applied to the package of the application processor in smart phone, and the reliability of the package was evaluated using thermal cycling reliability tests and numerical analysis. In order to find the optimal solid epoxy material and process conditions for improving the reliability, the effects of various factors on the reliability, such as the application number of solid epoxy, type of PCB pad, and different solid epoxy materials, were investigated. The reliability test results indicated that the package with solid epoxy exhibited higher reliability than that without solid epoxy. The application of solid epoxy at six locations showed higher reliability than that of solid epoxy at four locations indicating that the solid epoxy plays a role in relieving stress of the package, thereby improving the reliability of the package. For the different types of PCB pad, NSMD (non-solder mask defined) pad showed higher reliability than the SMD (solder mask defined) pad. This is because the application of the NSMD pad is more advantageous in terms of thermomechanical stress reliability because the solderpad bond area is larger. In addition, for the different solid epoxy materials with different thermal expansion coefficients, the reliability was more improved when solid epoxy having lower thermal expansion coefficient was used.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.188-190
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• 2004

As an effort to reduce cost and lead-time and to increase flexibility and responsiveness, manufacturers are using digital printing in numerous process steps. Typically, these processes require the precise dispensing of various fluids. Piezo ink jet printheads are proving to be reliable tools for depositing active materials such as light emitting polymers (LEP) for mobile phone displays and color filter inks for liquid crystal displays. Ink jets are also being used to provide uniform coatings of polyimide alignment layers and spacers for LCDs. Success with legend printing on PCBs using ink jets has encouraged the design of equipment for directly printing both etch resist and solder mask for PCBs. Development of printers for passive components such as capacitors and resistors is underway. This paper will present the attributes of an ink jet printhead designed to a precision deposition tool and discuss how it is being used to digitally print electronic and flat panel display components. Status of commercialization of digital printing will be discussed along with issues to be resolved before wide adoption takes place.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.19-27
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• 2003

Surface finishes of PCB laminates are important in the solder joint reliability of flip chip package because the types and thicknesses of intermetallic compound(IMC), and compositions and hardness of solders are affected by them. In this study, effects of surface finishes of PCB on the low cycle fatigue resistance of Sn-based lead-free solders; Sn-3.5Ag, Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag-XBi(X=2.5, 7.5) and Sn-0.7Cu were investigated for the Cu and Au/Ni surface finish treatments. Displacement controlled room temperature lap shear fatigue tests showed that fatigue resistance of Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag and Sn-0.7Cu alloys were more or less the same each other but much better than that of Bi containing alloys regardless of the surface finish layer used. In general, solder joints on the Au/Ni finish showed better fatigue resistance than those on the Cu finish. Cross-sectional fractography revealed microcracks nucleation inside of the interfacial IMC near the solder mask edge, more frequently on the Cu than the Au/Ni surface finish. Macro cracks followed the solder/IMC interface in the Bi containing alloys, while they propagated in the solder matrix in other alloys. It was ascribed to the Bi segregation at the solder/IMC interface and the solid solution hardening effect of Bi in the $\beta-Sn$ matrix.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.421-421
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• 2008

Generally, the polymer thick-film resistors for embedded organic or hybrid substrate are patterned by screen printing so that the accuracy of resistor pattern is not good and the tolerance of resistance is too high(${\pm}$20~30%). To reform these demerits, a method using Fodel$^{(R)}$ technology, which is the patterning method using a photosensitive resin to be developable by aqueous alkali-solution as a base polymer for thick-film pastes, was recently incorporated for the patterning of thermosetting thick-film resistor paste. Alkali-solution developable photosensitive resin system has a merit that the precise patterns can be obtained by UV exposure and aqueous development, so the essential point is to get the composition similar to PSR(photo solder resist) used for PCB process. In present research, we made the photopatternable resistor pastes using 8 kinds of epoxy acrylates and a conductive carbonblack (CDX-7055 Ultra), evaluated their developing performance, and then measured the resistance after final curing. To become developable by alkali-solution, epoxy acrylate oligomers with carboxyl group were prepared. Test coupons were fabricated by patterning copper foil on FR-4 CCL board, plating Ni/Au on the patterned copper electrode, applying the resistor paste on the board, exposing the applied paste to UV through Cr mask with resistor patterns, developing the exposed paste with aqueous alkali-solution (1wt% $Na_2CO_3$), drying the patterned paste at $80^{\circ}C$ oven, and then curing it at $200^{\circ}C$ during 1 hour. As a result, some test compositions couldn't be developed according to the kind of oligomer and, in the developed compositions, the measured resistance showed different results depending on the paste compositions though they had the same amount of carbonblack.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.