• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.48.1-48.1
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• 2011

In this presentation, We monitored weather data, such as global irradiance, ambient temperature, temperature of PV module, relative humidity and windspeed for 2 years, for determining accelerated test condition. then, we determined the temperature limit of accelerated test through weather data and FEM analysis. Detailed procedures will be summarized in this work. After analysing outdoor stress such as thermal stress, we decided main failure modes and mechanisms of PV module, especially solder joint of ribbon wire. we carried out the measurement of material properties such as thermal expansion coefficient for planning of accelerated test. we designed accelerated test based on FEM analysis results. we carried out thermal cycling test with 1 cell mini module for 3 months. We monitored the change of electrical performance every 1 week such as Voc, Isc, Pmax, etc. and then, we analized the ribbon wire/electrode intefaces. Detailed results will be summarized in this work.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.218-220
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• 2006

Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.19-27
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• 2003

Surface finishes of PCB laminates are important in the solder joint reliability of flip chip package because the types and thicknesses of intermetallic compound(IMC), and compositions and hardness of solders are affected by them. In this study, effects of surface finishes of PCB on the low cycle fatigue resistance of Sn-based lead-free solders; Sn-3.5Ag, Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag-XBi(X=2.5, 7.5) and Sn-0.7Cu were investigated for the Cu and Au/Ni surface finish treatments. Displacement controlled room temperature lap shear fatigue tests showed that fatigue resistance of Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag and Sn-0.7Cu alloys were more or less the same each other but much better than that of Bi containing alloys regardless of the surface finish layer used. In general, solder joints on the Au/Ni finish showed better fatigue resistance than those on the Cu finish. Cross-sectional fractography revealed microcracks nucleation inside of the interfacial IMC near the solder mask edge, more frequently on the Cu than the Au/Ni surface finish. Macro cracks followed the solder/IMC interface in the Bi containing alloys, while they propagated in the solder matrix in other alloys. It was ascribed to the Bi segregation at the solder/IMC interface and the solid solution hardening effect of Bi in the $\beta-Sn$ matrix.

• Proceedings of the KWS Conference
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• 2008.05a
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• pp.11-11
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• 2008

• Journal of the Korean institute of surface engineering
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• v.35 no.4
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• pp.218-231
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• 2002

As the environmental regulation worldwide emerges, most notably in Europe and Japan, the elimination of Pb usage in electronic assemblies has been an important issue for microelectronics assembly due to the inherent toxicity of Pb. This has provided an impetus towards the development of Pb-free solders. A major factor affecting alloy selection is the melting point, since this will have a major impact on the other polymeric materials used in microelectronic assembly and encapsulation. Other important manufacturing issues are cost, availability, and wetting characteristics. Reliability related properties include mechanical strength, fatigue resistance, coefficient of thermal expansion and reactivity with substrate. In this article, Pb-free solder alloys have been proposed so far have been reviewed and are summarized.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.2
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• pp.225-231
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• 2012

Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.

• Korean Journal of Materials Research
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• v.4 no.3
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• pp.329-333
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• 1994

A large number of grain boundaries were seen to crack in near-eutectic solder joints of leadless ceramic chip carriers (LLCC's) during thermal cycling at temperature ranges from -$35^{\circ}C$ to +$125^{\circ}C$ with lhr time period. One potential explanation for this type of cracking might be the presence of embrittling species on the boundary. Although there do not appear to be any instances reported in the literature of solders being embrittled by small amounts of contaminating species, the possibility of such an occurrence exists. The potential presence of impurities located at crack surfaces was inspected using Scanning Auger Microprobe(SAM) and it was found that intergranular cracking could be accomplished by the oxidation of the grain boundary. A physical model for fatigue crack growth was introduced, in which grain boundary separation took place under oxidation facilitated by sliding.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.18 no.5
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• pp.449-454
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• 2009

This paper presents an experimental study on the failure characteristics of SnAgCu lead-free solder balls. To estimate the effect of Ag, three types of SnAgCu balls are first prepared by varying the weight percent of Ag(1.0, 3.0, 4.0 wt%) and then analyzed by reliability tests such as thermal shock, high speed ball shear, and drop tests. Thermal shock test reveals that the higher the weight percent of Ag is, the longer the fatigue lift becomes. To the contrary, high speed ball-shear test and drop test show that the shear strength and the fracture toughness of solder balls are inversely proportional to the weight percent of Ag, respectively, Reasons for these observations will be further investigated In the future work.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.669-670
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• 2010