• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.185-187
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• 2005

The reactor protection system is the most important function for the safe operation of nuclear powerplants (NPPs) in that such system protects a nuclear reactor tore whose damage can cause an enormous disaster to the nuclear facility and the public. A digital reactor protection system (DRPS) is being developed in KAERI for use in the newly-constructed NPPs and also for replacing the existing analog-type reactor Protection systems. In this paper, an software verification and validation (V&V) activities for DRPS, which are independent of the DRPS development processes, are described according to the software development life cycle. The main activities of DRPS V&V processes are the software planning documentations, the verification of software requirements specification (SRS) and software design specification (SDS), the verification of codes, the tests of the integrated software and system. Moreover, the software safety analysis and the software configuration management are involved in the DRPS V&V processes. All of the V&V activities are described, in detail, in this paper.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.659-664
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• 2008

The Railroad Safety Act's regulation reads as follows. "The Minister of Construction and Transportation may qualify and authorize the product to guarantee performance and safety of parts, machine, and device used in Railway fields." Another regulation reads as follows."“The guidelines about targets, standards, and procedures of Quality and Authority in first provision are decided as Ministry of Construction and Transportation Decree." The software used in rail cars and facilities is considered as a railway product. Therefore, it is qualified and authorized for acquiring the safety of rail cars and facilities. The software businesses shall again a Quality and Authority for applying a software to the rail cars and facilities. This paper regulates some guidelines that are needed to develop a software. The procedures that a software developer performs are divided by plan, requirement, design, implementation, and maintenance. The procedures that a software verification person performs are classified by verification plan, requirement verification, design verification, implementation verification, testing verification, maintenance verification, and safety activity. The entire processes and detailed activities to develope and verify a software are described as new guidelines.

• Nuclear Engineering and Technology
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• v.28 no.6
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• pp.594-601
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• 1996

To assure quality of safety critical software, software should be developed in accordance with software development procedures and rigorous software verification and validation should be performed. Software verification is the formal act of reviewing, testing or checking, and documenting whether software components comply with the specified requirements for a particular stage of the development phase [1]. New software verification methodology was developed and was applied to the Shutdown System No. 1 and 2(SDS1,2) for Wolsong 2, 3 and 4 nuclear power plants by Korea Atomic Energy Research Institute(KAERI) and Atomic Energy of Canada Limited(AECL) in order to satisfy new regulation requirements of Atomic Energy Control Board(AECB). Software verification methodology applied to SDS1 for Wolsong 2, 3 and 4 project will be described in this paper. Some errors were found by this methodology during the software development for SDS1 and were corrected by software designer. Output from Wolsong 2, 3 and 4 project have demonstrated that the use of this methodology results in a high quality, cost-effective product.

• International Journal of Safety
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• v.3 no.1
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• pp.38-46
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• 2004

This paper introduces the software life-cycle V&V (verification and validation) tasks for the KNICS (Korea nuclear instrumentation and control system) project. The objectives of the V&V tasks are mainly to develop a programmable logic controller (PLC) for safety critical instrumentation and control (I&C) systems, and then to apply the PLC to developing the prototype of an engineered safety features-component control system (ESF-CCS) in nuclear power plants. As preparative works for the software V&V, various kinds of software plans and V&V task procedures have been developed according to the software life-cycle management. A number of software V&V tools have been adopted or developed to efficiently support the V&V tasks. The V&V techniques employed in this work include a checklist-based review and inspection, a requirement traceability analysis, formal verification, and life-cycle based software testing.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.3
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• pp.59-68
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• 2006

Recently, introduction of Open Source Software into informatization of the government and public sector has been actively examined, however, Open Source Software is being rarely adopted due to the lack of verified and reliable data with regard to the criteria, process, performance and stability for introduction of Open Source Software. In this paper, the process, method and plan for performance verification for introduction of Open Source Software into mission critical systems of the government and public sector are suggested in order to solve the aforesaid problem Specially, a test system to judge whether or not to adopt Open Source Software in school affairs system of the NEIS(National Education Information System) of the Korean government was set up, and the method and process of performance verification by stage in addition to feasibility study were applied to the test system for verification. Based on the result of performance evaluation in the test system, the application of Linux to school affairs system of the NEIS is being successfully practiced. It is expected that this study will be a guideline to technical review process and performance verification method as necessary to introduce Open Source Software into the mission critical systems of government and public agencies.

• Journal of the Korea Society for Simulation
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• v.18 no.3
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• pp.113-122
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• 2009

Software is getting more complex due to a variety of requirements that include desired functions and properties. Therefore, verifying and testing the software are complicated problems. Moreover, if the software is already implemented, inserting and deleting tracing/logging code into the source code may cause several problems, such as the code tangling and the code scattering problems. This paper proposes the Aspect DEVS Verification Framework which supports the verification and testing process. The Aspect DEVS Verification Framework utilizes Aspect Oriented Programming features to handle the code tangling and the code scattering problems. By applying aspect oriented features, a user can find and fix the inconsistency between requirement and implementation of a software without suffering the problems. The first step of the verification process is the building aspect code to make a software act as a generator. The second step is developing a requirement specification using DEVS diagrams and implementing it using the DEVSIM++. The final step is comparing the event traces from the software with the possible execution sequences from DEVS model.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.65-68
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• 2002

The verification of software part and HW/SW interface suffer from the absence of the hardware platform at the end of partitioning and coding phase in design cycle. In this paper we present the design of easy verification for hardware design. Hardware and software engineer can verify their software program and hardware design for a chip that is emulated in proposed verification environment. Besides, designer can easily design the DEMO system.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.6
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• pp.329-338
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• 2019

Today's embedded software (SW) developments are mostly preceded by composing Software Requirement Specification (SRS). In particular, in the domain of weapon systems, it is essential to have a systematic method for the verification of the SW functionality. To be more specific, it is crucial to check if the SW functionality is implemented as described in SRS, so-called SW suitability verification. Unfortunately, existing static or dynamic SW testing methods are not sufficient to evaluate suitability with SRS since those testings only verify the robustness of the SW codes. In this paper, we propose an automatic embedded SW suitability verification framework which is based on a structured SRS. The major challenge in the automation of this verification framework is how to get rid of ambiguities in SRS. In order to overcome this challenge, we propose a structured SRS description framework and the supporting toolchain for that. We show how the proposed framework is applied to an actual SRS of a weapon system.

• Journal of the Korea Society of Computer and Information
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• v.27 no.5
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• pp.109-116
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• 2022

Recently, a model-based development method centered on highly readable and standardized UML (Unified Modeling Language) models has been applied to solve unclear communications in large-scale software development. However, it is difficult to apply consistent UML models depending on software developers' proficiency, understanding of models and modeling tools. In this paper, we propose a method for developing a Model Verification System to apply an consistent UML model to software development. Then, the developed Model Verification System is partially applied to the Naval Combat System Software development to prove its function. The Model Verification System provides automatic verification of models created by developers according to domain characteristics. If the Model Verification System proposed in this paper is used, It has the advantage of being able to apply the consistent UML model more easily to Naval Combat System Software Development.