• Journal of Korean Society for Quality Management
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• 제26권1호
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• pp.99-107
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• 1998

This paper presents a software reliability model that is based on a nonhomogeneous poisson process. The major contribution of this model is combining multiple failure types with imperfect debugging by use of S-shaped mean value function. The software reliability model allows for three different types of errors: Critical errors are the most difficult to detect and the most expensive to remove. Major errors are moderately difficult to detect and fairly expensive to remove. Minor errors are easy to detect and inexpensive to remove. The model also allows for the introduction of any of these types of errors during the removal of an error. A numerical example is provided to illustrate the above techniques.

• The KIPS Transactions:PartA
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• 제17A권3호
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• pp.153-158
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• 2010

Most of software developers use the GNU Debugger (GDB) in order to debug code execution. The GDB supports a remote debugging environment through serial communication. However, in embedded systems, the speed is limited in the serial communication. Due to this reason, the serial communication is rarely used for the debugging purpose. To solve this problem, many embedded systems adapt the JTAG and the USB interface. This paper proposes debugging environment via USB-JTAG interface to debug the EISC processor, and introduces how the USB interface works on the GDB and how the JTAG module handles debugging packets.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 대한산업공학회/한국경영과학회 1992년도 춘계공동학술대회 발표논문 및 초록집; 울산대학교, 울산; 01월 02일 May 1992
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• pp.203-203
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• 1992

• The KIPS Transactions:PartD
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• 제11D권7호
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• pp.1491-1498
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• 2004

Successful project planning relics on a good estimation of the manpower required to complete a project, together with the schedule options that may be available. Despite the extensive research done developing new and better models, existing software manpower estimation models are present only the total manpower or instantaneous manpower distribution according to the testing time for the software life-cycle. This paper suggests the manpower estimating models for software testing phase as well as testing process and debugging process in accordance with de-tected faults. This paper presents the polynomial model for effort based on testing and debugging faults. These models are verified by 5 different software project data sets with coefficient of determination and mean magnitude of relative error for adaptability of model.

• Proceedings of the Safety Management and Science Conference
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• 대한안전경영과학회 2001년도 춘계학술대회
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• pp.77-81
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• 2001

Burn-in is a test procedure to find and eliminate the inherent initial failure of a product during or at the final stage of production process. Software testing is the validation and verification process which is used to cut off the faults from a software. The two have the common function and objective of "debugging". This article summarizes some significant models on the optimal hardware and software burn-in time, and provides the relevant paper lists. The need for the development of the unified burn-in policy of a hardware-software system is addressed.addressed.

• Journal of Information Technology Applications and Management
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• 제13권2호
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• pp.17-28
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• 2006

The SRGM has been studied under the assumption that S/W reliability can grow as the fault causing failure is removed even during operational phase because the debugging is available. On the other hand, some papers insist on the uniform failure rate during operational phase because the debugging may not be available in case of universal software. The phenomenon, however, has been observed informally many times that the products S/W reliability grows as the time goes by even without any debugging in point of customer view. I propose the simple approaching method to model the S/W reliability phenomenon that the failure rate reduces as time goes on without modifying the existing reliability model in this paper.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Journal of Korean Institute of Industrial Engineers
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• 제18권1호
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• pp.37-45
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• 1992

Common assumption we frequently encounter in early models of software reliability is that no new faults are introduced during the fault removal process. In real life, however, there are situations in which new faults are introducted as a result of imperfect debugging. This study alleviating this assumption by introducting the probability of perfect error-correction is an extension of Littlewood's work. In this model, the system reliability, failure rates, mean time to failure and average failure frequency are obtained. Here, when the probability of perfect error-correction is one, the results appear identical with those of the previous studies. In the respect that the results of previous studies are special cases of this model, the model developed can be considered as a generalized one.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 한국통신학회 2004년도 추계종합학술대회 논문 초록집
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• pp.268-268
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• 2004

• Journal of Advanced Navigation Technology
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• 제14권1호
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• pp.119-126
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• 2010

The software reliability growth model(SRGM) has been developed in order to estimate such reliability measures as remaining fault number, failure rate and reliability for the developing stage software. Almost of them assumed that the faults detected during testing were eventually removed. Namely, they have studied SRGM based on the assumption that the faults detected during testing were perfectly removed. The fault removing efficiency, however, is imperfect and it is widely known as so in general. It is very difficult to remove detected fault perfectly because the fault detecting is not easy and new error may be introduced during debugging and correcting. Therefore, We want to study imperfect software testing effort for the logistic testing effort which is thought to be the most adequate in this paper.