• The Bulletin of The Korean Astronomical Society
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• v.42 no.2
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• pp.85.1-85.1
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• 2017

We develop a coronagraph to measure the coronal electron density, temperature, and speed by observing the linearly polarized brightness of solar corona with 4 different wavelengths. Through the total solar eclipse on 21 August 2017, we test an operating software of a prototype coronagraph working with two sub-systems of two motorized filter wheels and a CCD camera that are controlled by a portable embedded computer. A Core Flight System (CFS) is a reusable software framework and set of reusable software applications which take advantage of a rich heritage of successful space mission of NASA. We use the CFS software framework to develop the operating software that can control the two sub-systems asynchronously in an observation scenario and communicate with a remote computer about commands, housekeeping data through Ethernet. The software works successfully and obtains about 160 images of 12 filter sets (4 bandpass filters and 3 polarization angles) during the total phase of the total solar eclipse. For the future, we can improve the software reliability by testing the software with a sufficient number of test cases using a testing framework COSMOS. The software will be integrated into the coronagraph for balloon-borne experiments in 2019.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.1
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• pp.75-80
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• 2010

Noise handing is very important in voice recognition of vehicle environment. that has been studying about to hardware and software approach. hardware method that is noise filter circuit design, basically using Low-pass filter. it was shown a good result. and the side of software that has been developing about to algorithm for Noise canceler, NN(neural network), etc. in this paper we have analysis about to classified parameter pattern matting level for voice recognition on car noise environment that use of DTW(Dynamic Time Warping) which is applicable time series pattern recognition algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.10
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• pp.1434-1440
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• 2014

This paper describes a demosaicking method for hexagonally-structured color filter array. Demosaicking is essential to acquire color images using color filter array (CFA) in single sensor imaging. Thus, CFA patterns have been discussed in order to improve image quality in single sensor imaging after the Bayer pattern are introduced. Advancements in imaging sensor technology recently introduce a hexagonal CFA pattern. The hexagonal CFA can be considered to be a 45-degree rotational version of the Bayer pattern, thus demosaicking can be implemented by an existing method with backward and forward 45-degree rotations. However, this approach requires heavy computing power and memory in image sensing devices because of the image rotations. To overcome this problem, we proposes a demosaicking method for a hexagonal Bayer CFA without rotations. In addition, we introduce a weighting parameter in our demosaicking method to improve image quality and to unifying exiting method with our method. Experimental results indicate that the proposed method is superior to conventional methods in terms of PSNR. In addition, some optimized values for the weighting parameter are provided experimentally.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.62-70
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• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• The Journal of Information Technology
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• v.9 no.1
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• pp.33-39
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• 2006

This study is for the contents of development to the hardware system and software driving algorithm to implement the frequency band of about 7KHz los pass digital filter which has the cut-off frequency of 392Hz by interfacing of a microprocessor with its peripheral analog-to-digital converter chip and digital-to-analog converter chip. The simplicity of digital filter design without difficulty and the implementation of programmed digital filter can be realized by providing the interfacing method to implement the law pass digital filter for the biological signals and the realization method of computer algorithm by a microprocessor.

• The Journal of Korean Institute of Next Generation Computing
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• v.14 no.5
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• pp.60-70
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• 2018

A software defined storage (SDS) is being deployed in cloud environment to allow multiple users to virtualize physical servers, but a solution for optimizing space efficiency with limited physical resources is needed. In the conventional data deduplication system, it is difficult to deduplicate redundant data uploaded to distributed storages. In this paper, we propose a distributed deduplication method using similarity-based clustering and multi-layer bloom filter. Rabin hash is applied to determine the degree of similarity between virtual machine servers and cluster similar virtual machines. Therefore, it improves the performance compared to deduplication efficiency for individual storage nodes. In addition, a multi-layer bloom filter incorporated into the deduplication process to shorten processing time by reducing the number of the false positives. Experimental results show that the proposed method improves the deduplication ratio by 9% compared to deduplication method using IP address based clusters without any difference in processing time.

• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.185-190
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• 2006

JPEG 2000 is used as an alternative to solve the blocking artifact problem with the existing still image compression JPEG algorithm. However, it has shortcomings such as longer floating point computation time and more complexity in the procedure of enhancing the image compression rate and decompression rate. To compensate for these we implemented with hardware the JPEG 2000 algorithm's filter part which requires a lot of floating point computation. This DWT Filter[1] chip is designed on the basis of Daubechies 9/7 filter[6] and is composed of 3-stage pipeline system to optimize the performance and chip size. Our implemented Filter was 7 times faster than software based Filter in the floating point computation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.2
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• pp.687-701
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• 2020

In the production of industrial fabric, it needs automatic real-time system to detect defects on the fabric for assuring the defect-free products flow to the market. At present, many visual-based methods are designed for detecting the fabric defects, but they usually lead to high false alarm. Base on this reason, we propose a Sobel operator combined with patch statistics (SOPS) algorithm for defects detection. First, we describe the defect detection model. mean filter is applied to preprocess the acquired image. Then, Sobel operator (SO) is applied to deal with the defect image, and we can get a coarse binary image. Finally, the binary image can be divided into many patches. For a given patch, a threshold is used to decide whether the patch is defect-free or not. Finally, a new image will be reconstructed, and we did a loop for the reconstructed image to suppress defects noise. Experiments show that the proposed SOPS algorithm is effective.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.41-52
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• 2011

It is important to reduce computational complexity of de-blocking filter for real-time implementation, because it accounts for a great part of total computational complexity of the decoder. Because there are a lot of conditional branches and memory accesses in a decoding loop, it is not easy to speed up the de-blocking filter. Therefore, this paper presents a new algorithm of de-blocking filter minimizing conditional branches and memory accesses. The proposed structure of de-blocking filter enables filter operation to parallelize by software pipelining. The proposed optimization method was implemented on a TMS320DM6467 EVM board and we achieved approximately 46% cycle reduction, compared with that of FFmpeg.