• Journal of the Korea Society of Computer and Information
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• v.28 no.1
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• pp.71-78
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• 2023

In this paper, we analyze the structure of TV video software, one of the warship combat management system software, and propose a standard architecture that minimizes software modification due to the discontinuation replacement of warship hardware. The class structure was newly designed to minimize the class modified when replacing the warship hardware by separating the variable elements and common elements of TV video software through FORM(Feature-Oriented Reuse Method), the common part that communicates with the warship combat management system and displays the TV screen and the variable part that communicates between the operator and the TV camera. In addition, the Strategy design pattern is applied to efficiently add and modify classes that directly use hardware-dependent APIs when replacing hardware discontinuation, and to make both discontinued and replacements available software. Finally, the reliability testing time and functional testing time of the existing TV video software and the proposed software were measured and compared, and finally, it was confirmed that the hardware discontinuation replacement cost was reduced.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.6
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• pp.990-997
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• 2010

The Mission environment of UGV(Unmanned Ground Vehicle) has a complexity and variety, and the status of system and sensor is dependent on the environment factors such as operation time, the weather and road type. It is necessary for UGV to cope adaptively with the various mission types, operation modes and operation environment as human operators do. To satisfy this necessity, we present an autonomy manager based on the autonomous architecture. In this paper, we design a path planning software architecture and LPP manager by using open autonomous architecture which is previously designed by ADD. Field test is conducted with UGV in order to verify the performance of LPP Manager based on the Autonomous Architecture with scenarios.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.4
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• pp.611-617
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• 2008

In ubiquitous environments, the content adaptable services can be dynamically provided to adapt the frequent changes of contexts. These services have common things that the kinds of context factors are limited to ubiquitous environment, though the contexts are flexible. To reuse service architecture can be reasonable for effective adaptable service. In this paper, we design a software architecture with product line techniques for content adaptable applications in ubiquitous environment. Description of product line is to define variation points and their variants, to find out the dependencies between them and to keep the model based architecture, their alternatives.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Proceedings of the KIEE Conference
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• 2000.11b
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• pp.389-391
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• 2000

A representation technique of a given track topology is required by many software applications in railway technology such as signalling system simulator. To achieve these, the concept of double vertex graph architecture is proposed. These are composed of pairs of vertices and node between the single vertices. Double vertex graph architecture can be understood as a extension of classical graphs. In developed railway signalling simulation software, it is shown that track topology can be represented by proposed algorithm in a efficient way. Especially it makes sure that these are suitable technique for representing and implementing of switch, routes which can be introduced some mistake in classical graph algorithm.

• Proceedings of the Korean Society of Computer Information Conference
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• 2022.01a
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• pp.349-351
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• 2022

본 논문에서는 계산양이 큰 볼륨 렌더링을 구현할 수 있는 파이썬 기반의 CUDA(Computed Unified Device Architecture) 커널(Kernel) 디자인에 대해서 소개한다. 최근에 파이썬은 인공지능뿐만 아니라 서버, 보안, GUI, 데이터 시각화, 빅 데이터 처리 등 다양한 분야에서 활용이 되고 있기 때문에 인터페이스만을 위한 언어라는 색을 탈피한지 오래이다. 본 논문에서는 대용량 병렬처리 기법인 NVIDIA의 CUDA를 이용하여 파이썬 환경에서 커널을 디자인하고, 계산양이 큰 볼륨 렌더링이 빠르게 계산되는 결과를 보여준다. 결과적으로 C언어 기반의 CUDA뿐만 아니라, 상대적으로 개발이 효율적인 파이썬 환경에서도 GPU(Graphic Processing Unit)기반 애플리케이션 개발이 가능하다는 것을 볼륨 렌더링을 통해 보여준다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.799-802
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• 1999

In this paper, programmable abstractions of the underlying resources of the IP router are proposed for designing a software architecture of the next generation router, which can provide the variety of QoS services and reliable and complicate network services.

• ETRI Journal
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• v.11 no.1
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• pp.136-144
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• 1989

This paper presents the interworking services and the call connection procedures in the PSTN-PSDN(Public Switched Telephone Network-Packet Switched Data Network) Interworking System(IWS). Also the architecture and design for the software and hardware in IWS are described.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

• International conference on construction engineering and project management
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• 2011.02a
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• pp.74-83
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• 2011

This paper recognized a need in the architecture, engineering, and construction industry for new programs and methods of producing reliable energy simulations using BIM (Building Information Modeling) technology. Current methods and programs for running energy simulations are not very timely, difficult to understand, and lack high interoperability between the BIM software and energy simulation software. It is necessary to improve on these drawbacks as design decision are often made without the aid of energy modeling leading to the design and construction of non-optimized buildings with respect to energy efficiency. The goal of this research project is to develop a new methodology to produce energy estimates from a BIM model in a more timely fashion and to improve interoperability between the simulation engine and BIM software. In the proposed methodology, the extracted information from a BIM model is compiled into an INP file and run in a popular energy simulation program, DOE-2, on an hourly basis for a desired time period. Case study showed that the application of this methodology could be used to expediently provide energy simulations while at the same time reproducing the BIM in a more readably three dimensional modeling program. With the aid of an easy to run and easily understood energy simulation methodology, designers will be able to make more energy conscious decisions during the design phase and as changes in design requirements arise.