• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.671-676
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• 2003

This paper presents 3-phase current regulation of SR motor by only single current sensor. The conventional drive system of SR motor has a current sensor per each phase. In this paper, The asymmetric bridge converter which Is able to control independently phases and be excited simultaneously is used fs the driver system for 6/4 poles SR motor. And the sensor Is replaced 3 sensors of each phase with only one on bus line of converter so as to detect current of every phase. A drive logic circuit is designed on EPLD with Delta modulation using a fixed frequency This technique is verified through simulation and experiment.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.25-30
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• 2017

Arago's disk system consists of a speed controller of the DC motor (inner loop controller) and a position controller of the magnetic bar angle (main controller), which are implemented by the design of the PI and PID controller, respectively. First, we analyzed the nonlinear characteristics of the Arago disk system and found the operating point range of three locations as a result. In this paper, a gain scheduler method was applied to guarantee a constant control performance in the range of $0{\sim}130^{\circ}C$, and a structure to change the controller according to the control reference value based on the previously obtained operating points was experimentally implemented. The Distributed Control Systems (DCS) configuration using the Controller Area Network (CAN) was used to verify the proposed method by improving the operational efficiency of the entire experimental system. So, simplicity of the circuit and easy diagnosis were achieved through a single CAN bus communication.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Journal of IKEEE
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• v.24 no.2
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• pp.486-491
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• 2020

ARM Cortex-M0 DesignStart provided by ARM is cost-free design development suit targeting for designing and prototyping SoC with Cortex-M0 core. In this paper, we presents a method how to implement a custom system design using ARM Cortex-M0 DesignStart. First, hardware elements for ARM Cortex-M0 DesginStart is analyzed focusing on bus and memory map, and next software toolchain is explained to clarify the translating process from high level language to binary machine language. As an example of the custom system, UART system operated with Cortex-M0 is designed and simulated.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.474-479
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• 2014

LEON3 is a 32-bit synthesizable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7- stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the debugging tool for LEON3 based embedded systems. The debugging tool can initialize the target hardware, find out how the target hardware is configured, load application code to a specified memory space and run that application code. To provide users a debugging environment, it can set breakpoints and control the operation of LEON3 correspondingly. And function call trace is one of key functions of the debugging tool.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.881-888
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• 2006

The position of the bridged tap is determined by that of the outlet in most modern apartments, since most of the indoor wiring utilizes the bus wiring structure when deploying the indoor communication line. These bridged taps deteriorate transmission performance in the specific frequency at the time of high-speed multimedia communication, which uses a high frequency bandwidth, since the duality of return loss worsens and line attenuation increases rapidly. As a result, analysis on this phenomenon is required. In this study, the test model is created by modeling the intercommunication facility of the apartment that is the most representative residential house type, and by understanding the structure and the environment of the indoor wiring. Also, how the bridge tap affects performance is analyzed when the VDSL service is provided, so that problems of intercommunication lines can be identified and methods for improving the proper intercommunication line can be suggested, which is suitable for accommodating high-speed multimedia service of the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.